データシートサーチシステム |
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AK5556VN データシート(PDF) 24 Page - Asahi Kasei Microsystems |
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AK5556VN データシート(HTML) 24 Page - Asahi Kasei Microsystems |
24 / 69 page [AK5556] 015099857-E-00 2016/03 - 24 - (Ta= 40 - +105 C; AVDD= 4.5-5.5 V, TVDD= 1.7-1.98 V (LDOE pin=“L”) or 3.0-3.6 V (LDOE pin=“H”), VDD18= 1.7-1.98 V (LDOE pin=“L”), C L= 10 pF) Parameter Symbol Min. Typ. Max. Unit Audio Interface Timing (Master mode) (Figure 23) DSD Audio Interface Timing (64fs mode, DSDSEL 1-0 bits = “00”) DCLK Period DCLK Pulse Width Low DCLK Pulse Width High DCLK Edge to DSDOL/R (Note 20) tDCK tDCKL tDCKH tDDD - 144 144 20 1/64fs - - - - - - 20 ns ns ns ns DSD Audio Interface Timing (128fs mode, DSDSEL 1-0 bits = “01”) DCLK Period DCLK Pulse Width Low DCLK Pulse Width High DCLK Edge to DSDOL/R (Note 20) tDCK tDCKL tDCKH tDDD - 72 72 10 1/128fs - - - - - - 10 ns ns ns ns DSD Audio Interface Timing (256fs mode, DSDSEL 1-0 bits = “10”) DCLK Period DCLK Pulse Width Low DCLK Pulse Width High DCLK Edge to DSDOL/R (Note 20) tDCK tDCKL tDCKH tDDD - 36 36 10 1/256fs - - - - - - 10 ns ns ns ns Note 18. When the 1024fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK5556 should be reset by the PDN pin or RSTN bit. Note 20. tDDD is defined from a falling edge of DCLK “↓” to a DSDOL/R edge when DCKB bit = “0” and it is defined from a rising edge of DCLK “↑” to a DSDOL/R edge when DCKB bit = “1”. |
同様の部品番号 - AK5556VN_16 |
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同様の説明 - AK5556VN_16 |
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