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AK5556VN データシート(PDF) 25 Page - Asahi Kasei Microsystems |
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AK5556VN データシート(HTML) 25 Page - Asahi Kasei Microsystems |
25 / 69 page [AK5556] 015099857-E-00 2016/03 - 25 - (Ta= 40 - +105 C; AVDD= 4.5-5.5 V, TVDD= 1.7-1.98 V (LDOE pin=“L”) or 3.0-3.6 V (LDOE pin=“H”), VDD18= 1.7-1.98 V (LDOE pin=“L”), C L= 10 pF) Note 21. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 22. The AK5556 can be reset by setting the PDN pin to “L” upon power-up. The PDN pin must held “L” for more than 150 ns for a certain reset. The AK5556 is not reset by the “L” pulse less than 30 ns. Note 23. This cycle is the number of LRCK rising edges from the PDN pin = “H”. Parameter Symbol Min. Typ. Max. Unit Control Interface Timing (3-Wire Serial mode): (Figure 25) (Figure 26) CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Timing CDTI Hold Timing CSN “H” Time CSN “↓” to CCLK “↑” CCLK “↑” to CSN “↑” tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 80 80 40 40 150 50 50 - - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns Control Interface Timing (I 2C Bus mode): (Figure 27) SCL CLOCK Frequency Bus Free Time Between Transmissions Start Condition Hold Tune (Prior to First Clock Pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 21) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter Capacitive Load on Bus fSCL tBUF tHD STA tLow tHIGH tSU STA tHD DAT tSU DAT tR tF tSU STO tSP Cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 - - - - - - - - - - - - - - 400 - - - - - - - 1.0 0.3 - 50 400 kHz µs µs µs µs µs µs µs µs µs µs ns pF Power Down & Reset Timing (Figure 28) PDN Pulse Width (Note 22) PDN Reject Pulse Width (Note 22) PDN “↑” to SDTO1-4 valid (Note 23) tPD tRPD tPDV 150 - - - - 583 - 30 - ns ns 1/fs |
同様の部品番号 - AK5556VN_16 |
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同様の説明 - AK5556VN_16 |
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