データシートサーチシステム |
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PC87311A データシート(PDF) 3 Page - National Semiconductor (TI) |
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PC87311A データシート(HTML) 3 Page - National Semiconductor (TI) |
3 / 78 page Table of Contents 634 Line Status Register (LSR) 56 635 FIFO Control Register (FCR) 57 636 Interrupt Identification Register (IIR) 57 637 Interrupt Enable Register (IER) 57 638 MODEM Control Register (MCR) 58 639 MODEM Status Register (MSR) 59 6310 Scratchpad Register (SCR) 59 70 PARALLEL PORT 59 71 Introduction 59 72 Data Register (DTR) 60 73 Status Register (STR) 60 74 Control Register (CTR) 60 80 INTEGRATED DEVICE ELECTRONICS INTERFACE (IDE) 61 81 Introduction 61 82 IDE Signals 61 90 DEVICE DESCRIPTION 62 91 DC Electrical Characteristics 62 92 AC Electrical Characteristics 64 921 AC Test Conditions 64 922 Clock Timing 64 923 Microprocessor Interface Timing 65 924 Baudout Timing 66 925 Transmitter Timing 67 926 Receiver Timing 68 927 MODEM Control Timing 69 928 DMA Timing 70 929 Reset Timing 71 9210 Write Data Timing 71 9211 Drive Control Timing 72 9212 Read Data Timing 72 9213 IDE Timing 72 9214 Parallel Port Timing 73 100 REFERENCE SECTION 74 101 Mnemonic Definitions for FDC Commands 74 102 Example Four Drive Circuit Using the PC87311A12 75 List of Figures FIGURE 2-1 PC87311A87312 Configuration Registers 12 FIGURE 3-1 FDC Functional Block Diagram 18 FIGURE 4-1 IBM Perpendicular and ISO Formats Supported by Format Command 30 FIGURE 5-1 FDC Data Separator Block Diagram 44 FIGURE 5-2 PC87311A87312 Dynamic Window Margin Performance 45 FIGURE 5-3 Read Data AlgorithmState Diagram 46 FIGURE 5-4 Perpendicular Recording Drive RW Head and Pre-Erase Head 46 FIGURE 6-1 PC87311A Composite Serial Data 48 FIGURE 6-2 PC87312 Composite Serial Data 54 FIGURE 9-1 Clock Timing 64 FIGURE 9-2 Microprocessor Read Timing 65 FIGURE 9-3 Microprocessor Write Timing 66 FIGURE 9-4 Baudout Timing 66 FIGURE 9-5 Transmitter Timing 67 FIGURE 9-6a Receiver Timing 68 FIGURE 9-6b PC87312 FIFO Mode Receiver Timing 68 FIGURE 9-6c PC87312 Timeout Receiver Timing 69 FIGURE 9-7 MODEM Control Timing 69 FIGURE 9-8 DMA Timing 70 FIGURE 9-9 Reset Timing 71 FIGURE 9-10 Write Data Timing 71 FIGURE 9-11 Drive Control Timing 72 FIGURE 9-12 Read Data Timing 72 FIGURE 9-13 IDE Timing 72 FIGURE 9-14 Parallel Port Interrupt Timing (Compatible Mode) 73 FIGURE 9-15 Parallel Port Interrupt Timing (Extended Mode) 73 FIGURE 9-16 Typical Parallel Port Data Exchange 73 FIGURE 10-1 PC87311A87312 Four Floppy Drive Circuit 75 FIGURE 10-2 IDE Interface Signal Equations 75 FIGURE 10-3 PC87311A87312 Adapter Card Schematic 76 3 |
同様の部品番号 - PC87311A |
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同様の説明 - PC87311A |
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