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TP11362A データシート(PDF) 11 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部品番号 TP11362A
部品情報  Quad Adaptive Differential PCM Processor
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メーカー  NSC [National Semiconductor (TI)]
ホームページ  http://www.national.com
Logo NSC - National Semiconductor (TI)

TP11362A データシート(HTML) 11 Page - National Semiconductor (TI)

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Timing Specifications (Continued)
Unless otherwise noted, limits printed in bold characters are guaranteed for V
CC = 5.0V ± 5%, GND1 = GND2 = 0V, TA =
−40˚C to +85˚C by correlation with 100% electrical testing at T
A = 25˚C. All other limits are assured by correlation with other
production tests and/or product design and characterization. Typical values are specified at V
CC = +5V, TA = 25˚C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
HDCEL
Hold Time, CE low after
From CE Low
15
ns
PSCK/ASCK High
t
SUCEH
Setup Time, CE High Before
From CE Low
15
ns
PSCK/ASCK Low
t
TRBH
TRB Hold Time
From CE Low
20
ns
t
TRBS
TRB Setup Time
From ASCK Low and PSCK Low
20
ns
t
IS
TSI, RSI Setup Time
From ASCK Low and PSCK Low
20
ns
t
IH
TSI, RSI Hold Time
From ASCK Low and PSCK Low
20
ns
t
PSCK/ASCK
PSCK/ASCK High and
55
ns
Low Times
t
ON
TSO, RSO Turn On Time
From CE High
40
ns
t
OD
TSO, RSO Propagation
From ASCK High or PSCK High
40
ns
Delay Time
t
OFF
TSO, RSO Turn Off Time
From CE Low
20
ns
(Valid Data to TRI-STATE)
t
CS
Setup Time for Control
From CE Low
Signals (INIT, EN,
20
ns
PCM1, QSEL1, QSEL0)
t
CH
Hold Time for Control
From CE Low
Signals (INIT, EN,
20
ns
PCM1, QSEL1, QSEL0)
t
RSTL
RSTB Pulse Width Low
2
CLK
Cycles
t
RSTH
RSTB High to the First
6
CLK
CE High-Low Transition
Cycles
Note 5: Values for 4 full-duplex (decoding and encoding) or 8 half-duplex (decoding or encoding) channels operation in a 125 µs period.
11
www.national.com


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