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74ALVCH16374T データシート(PDF) 1 Page - Fairchild Semiconductor |
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74ALVCH16374T データシート(HTML) 1 Page - Fairchild Semiconductor |
1 / 7 page © 2002 Fairchild Semiconductor Corporation DS500627 www.fairchildsemi.com September 2001 Revised February 2002 74ALVCH16374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold General Description The ALVCH16374 contains sixteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus ori- ented applications. The device is byte controlled. A buff- ered clock (CP) and output enable (OE) are common to each byte and can be shorted together for full 16-bit opera- tion. The ALVCH16374 data inputs include active bushold cir- cuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. The 74ALVCH16374 is designed for low voltage (1.65V to 3.6V) VCC applications with output compatibility up to 3.6V. The 74ALVCH16374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain- ing low CMOS power dissipation. Features s 1.65V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold on data inputs eliminates the need for external pull-up/pull-down resistors s tPD 4.2 ns max for 3.0V to 3.6V VCC 5.3 ns max for 2.3V to 2.7V VCC 7.8 ns max for 1.65V to 1.95V VCC s Uses patented noise/EMI reduction circuitry s Latch-up conforms to JEDEC JED78 s ESD performance: Human body model > 2000V Machine model > 200V Ordering Code: Note 1: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Order Number Package Number Package Descriptions 74ALVCH16374T (Note 1) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide |
同様の部品番号 - 74ALVCH16374T |
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同様の説明 - 74ALVCH16374T |
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