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FM24CL64 データシート(PDF) 2 Page - List of Unclassifed Manufacturers

部品番号 FM24CL64
部品情報  64Kb 2.7V-3.6V FRAM Serial Memory
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FM24CL64
Rev 2.0
July 2003
Page 2 of 14
Address
Latch
`
2,048 x 32
FRAM Array
Data Latch
8
SDA
Counter
Serial to Parallel
Converter
Control Logic
SCL
WP
A0-A2
Figure 1. FM24CL64 Block Diagram
Pin Description
Pin Name
Type
Pin Description
A0-A2
Input
Address 0-2. These pins are used to select one of up to 8 devices of the same type on
the same two-wire bus. To select the device, the address value on the three pins must
match the corresponding bits contained in the device address. The address pins are
pulled down internally.
SDA
I/O
Serial Data Address. This is a bi-directional line for the two-wire interface. It is
open-drain and is intended to be wire-OR’d with other devices on the two-wire bus.
The input buffer incorporates a Schmitt trigger for noise immunity and the output
driver includes slope control for falling edges. A pull-up resistor is required.
SCL
Input
Serial Clock. The serial clock line for the two-wire interface. Data is clocked out of
the part on the falling edge, and in on the rising edge. The SCL input also
incorporates a Schmitt trigger input for noise immunity.
WP
Input
Write Protect. When tied to VDD, addresses in the entire memory map will be write-
protected. When WP is connected to ground, all addresses may be written. This pin
is pulled down internally.
VDD
Supply
Supply Voltage: 2.7V to 3.6V
VSS
Supply
Ground


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