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X1443BIGABL データシート(PDF) 11 Page - Texas Instruments |
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X1443BIGABL データシート(HTML) 11 Page - Texas Instruments |
11 / 76 page 11 AWR1443 www.ti.com SWRS202 – MAY 2017 Submit Documentation Feedback Product Folder Links: AWR1443 Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated 4.2 Signal Descriptions Table 4-1. Signal Descriptions FUNCTION SIGNAL NAME PIN NUMBER PIN TYPE DESCRIPTION Transmitters TX1 B4 O Single-ended transmitter1 o/p TX2 B6 O Single-ended transmitter2 o/p TX3 B8 O Single-ended transmitter3 o/p Receivers RX1 M2 I Single-ended receiver1 i/p RX2 K2 I Single-ended receiver2 i/p RX3 H2 I Single-ended receiver3 i/p RX4 F2 I Single-ended receiver4 i/p LVDS TX LVDS_TXP[0] G15 O Differential data Out – Lane 0 LVDS_TXM[0] G14 O LVDS_CLKP J15 O Differential clock Out LVDS_CLKM J14 O LVDS_TXP[1] H15 O Differential data Out – Lane 1 LVDS_TXM[1] H14 O HS_RESERVED_TXP[2] K15 O Differential data Out – Lane 2 HS_RESERVED_TXM[2 ] K14 O HS_RESERVED_TXP[3] L15 O Differential data Out – Lane 3 HS_RESERVED_TXM[3 ] L14 O LVDS_FRCLKP M15 O Differential debug port 1 LVDS_FRCLKM M14 O HS_DEBUG2_P N15 O Differential debug port 2 HS_DEBUG2_M N14 O RESERVED B15, B1, D15, D1 System synchronization SYNC_OUT P11 O Low-frequency synchronization signal output SYNC_IN N10 I Low-frequency synchronization signal input SPI control interface from external MCU (default slave mode) SPI_CS_1 R7 I SPI chip select SPI_CLK_1 R9 I SPI clock MOSI_1 R8 I SPI data input MISO_1 P5 O SPI data output SPI_HOST_INTR_1 P6 O SPI interrupt to host RESERVED R3, R4, R5, P4 Reset NRESET P12 I Power on reset for chip. Active low WARM_RESET N12 IO Open-drain fail-safe warm reset signal. Can be driven from PMIC for diagnostic or can be used as status signal that the device is going through reset. Safety NERROR_OUT N8 O Open-drain fail-safe output signal. Connected to PMIC/Processor/MCU to indicate that some severe criticality fault has happened. Recovery would be through reset. NERROR_IN P7 I Fail-safe input to the device. Error output from any other device can be concentrated in the error signaling monitor module inside the device and appropriate action can be taken by firmware JTAG TMS L13 I JTAG port for standard boundary scan TCK M13 I TDI H13 I TDO J13 O |
同様の部品番号 - X1443BIGABL |
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同様の説明 - X1443BIGABL |
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