HT82V70 datasheet(17/71 Pages) HOLTEK

部品番号	HT82V70

部品情報	Two 6-Channel, up to 240MSPS CIS Timing Generator and Shading Correction

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メーカー	HOLTEK [Holtek Semiconductor Inc]

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17 / 71 page

Rev. 1.00

17

January 12, 2017

HT82V70

Register Description

Page 0 Register – System Setup

• Address P0_01h: Software Reset Register

Bit

Mode

Description

Default

7-2

—

Reserved

—

1

R/W

ISP Engine Software reset (Self clear)

1: Reset

0

R/W

TG Controller Software reset (Self clear)

1: Reset

0

• Address P0_02h: Mode Setting Register

Bit

Mode

Description

Default

7-5

—

Reserved

—

4

R/W

Register Mode Setting Enable

0: Disable

1: Enable

0

3-0

R/W

Register Mode Selection

4’h0: Normal mode

4’h1: Reserved

4’h2: DFT Test Mode

4’h3: Tie-High Test Mode

4’h4: Tie-Low Test Mode

4’h5: Nand-tree Test Mode

4’h6: Pull-Up-Down Test Mode

4’h7: Iptest Test Mode

4’h8: Debug1 Mode

4’h9: Debug2 Mode

4’ha: Debug3 Mode

0h

• Address P0_03h: Pixel Clock Configuration Register 0

Bit

Mode

Description

Default

7

—

Pixel Clock Enable

0: Disable

1: Enable

—

6-5

R/W

Input Clock selection, used with b7

00: OSC – 12Mhz

01: OSC – 12Mhz

10: PLL1 (96Mhz)

11: PLL2 (144Mhz)

0h

4

R/W

Clock Division Enable

0: Not Divided

1: Divided

0

3-0

—

Reserved

—

• Address P0_04h: Pixel Clock Configuration Register 1

Bit

Mode

Description

Default

7-6

—

Reserved

—

5-0

R/W

Clock Division Factor (DIV_FACT) [5:0]

Output clock = input_clock/ (DIV_FACT+2)

00h

Note:setP0_04firstandthensetP0_03hlatter.

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