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HT82V70 データシート(PDF) 33 Page - Holtek Semiconductor Inc |
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HT82V70 データシート(HTML) 33 Page - Holtek Semiconductor Inc |
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33 / 71 page  Rev. 1.00 33 January 12, 2017 HT82V70 Bit Mode Description Default 2-0 R/W CIS to ASIC Data Mapping Selection 000: 1-2-3-4 ASIC AFE_DIN[7:0] AFE_DIN[15:8] AFE2_DIN[7:0] AFE2_DIN[15:8] ↔ CIS (123) CIS (456) CIS2 (123) CIS2 (456) 001: 1-3-2-4 ASIC AFE_DIN[7:0] AFE_DIN[15:8] AFE2_DIN[7:0] AFE2_DIN[15:8] ↔ CIS (123) CIS2 (123) CIS (456) CIS2 (456) 010: 1-4-3-2 ASIC AFE_DIN[7:0] AFE_DIN[15:8] AFE2_DIN[7:0] AFE2_DIN[15:8] ↔ CIS (123) CIS2 (456) CIS2 (123) CIS (456) 011: 3-2-1-4 ASIC AFE_DIN[7:0] AFE_DIN[15:8] AFE2_DIN[7:0] AFE2_DIN[15:8] ↔ CIS2 (123) CIS (456) CIS (123) CIS2 (456) 100: 4-2-3-1 ASIC AFE_DIN[7:0] AFE_DIN[15:8] AFE2_DIN[7:0] AFE2_DIN[15:8] ↔ CIS2 (456) CIS (456) CIS2 (123) CIS (123) 101: 3-4-1-2 ASIC AFE_DIN[7:0] AFE_DIN[15:8] AFE2_DIN[7:0] AFE2_DIN[15:8] ↔ CIS2 (123) CIS2 (456) CIS (123) CIS (456) Others:Reserved 000 • Address P2_1Bh: AFE Data Output To ASIC Data Input Order Register Bit Mode Description Default 7 R/W ASIC AFE2_DIN[15:8] Bit Reverse 0: Normal 1: Reverse 0 6 R/W ASIC AFE2_DIN[7:0] Bit Reverse 0: Normal 1: Reverse 0 5 R/W ASIC AFE_DIN[15:8] Bit Reverse 0: Normal 1: Reverse 0 4 R/W ASIC AFE_DIN[7:0] Bit Reverse 0: Normal 1: Reverse Note: When bit reverse AFE_DIN[7:0] → AFE_DIN[0:7] 0 3-2 — Reserved — 1 R/W ASIC AFE2_DIN Byte Exchange 0: Normal 1: Exchange Note: When byte exchange AFE2_DIN[15:0] → {AFE2_DIN[7:0], AFE2_DIN[15:8]}. 0 0 R/W ASIC AFE_DIN Byte Exchange 0: Normal 1: Exchange Note: When byte exchange AFE_DIN[15:0] → {AFE_DIN[7:0], AFE_DIN[15:8]}. 0 • Address P2_1Ch: CIS Bypass Selection Register Bit Mode Description Default 7-3 — Reserved — 2 R/W Bypass Channel Number Selection 0: 1,2,3 channel 1: 4,5,6 channel 0 1 R/W Bypass Original 16-bit CIS Data Selection 0: CIS1 1: CIS2 Note: When bit 0 is enabled, P7_00 should be 8’h00, P9_00 should be 8’h00, P9_01 should be 8’h00, P9_02 should be 8’h00. 0 |
同様の部品番号 - HT82V70 |
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同様の説明 - HT82V70 |
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