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HT82K95E データシート(PDF) 10 Page - Holtek Semiconductor Inc |
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HT82K95E データシート(HTML) 10 Page - Holtek Semiconductor Inc |
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10 / 42 page  HT82K95E/HT82K95A Rev. 2.40 10 November 5, 2014 In addition, on entering the interrupt sequence or exe- cuting the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are important and if the subroutine can cor- rupt the status register, precautions must be taken to save it properly. Interrupt The device provides an external interrupt and internal timer/event counter interrupts. The Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set the enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other in- terrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain inter- rupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related in- terrupt is enabled, until the SP is decremented. If immedi- ate service is desired, the stack must be prevented from becoming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the pro- gram memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the con- tents should be saved in advance. USB interrupts are triggered by the following USB events and the related interrupt request flag (USBF; bit 4 of the INTC) will be set. · The corresponding USB FIFO is accessed from the PC · The USB suspends signal from the PC · The USB resumes signal from the PC · The USB sends Reset signal When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to loca- tion 04H will occur. The interrupt request flag (USBF) and EMI bits will be cleared to disable other interrupts. When the PC Host access the FIFO of the HT82K95E/ HT82K95A, the corresponding request bit of the USR is set, and a USB interrupt is triggered. So user can easily decide which FIFO is accessed. When the interrupt has been served, the corresponding bit should be cleared by firmware. When the HT82K95E/HT82K95A receives a USB Suspend signal from the Host PC, the suspend line (bit0 of the USC) of the HT82K95E/HT82K95A is set and a USB interrupt is also triggered. Also when the HT82K95E/HT82K95A receives a Re- sume signal from the Host PC, the resume line (bit3 of the USC) of HT82K95E/HT82K95A is set and a USB in- terrupt is triggered. Whenever a USB reset signal is detected, the USB in- terrupt is triggered. The internal Timer/Event Counter 0 interrupt is initial- ized by setting the Timer/Event Counter 0 interrupt re- quest flag (T0F; bit 5 of INTC), caused by a timer 0 overflow. When the interrupt is enabled, the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further in- terrupts. The internal Timer/Even Counter 1 interrupt is initialized by setting the Timer/Event Counter 1 interrupt request flag (T1F; bit 6 of INTC), caused by a timer 1 overflow. When the interrupt is enabled, the stack is not full and the T1F is set, a subroutine call to location 0CH will oc- cur. The related interrupt request flag (T1F) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other in- terrupt acknowledge signals are held until the ²RETI² in- struction is executed or the EMI bit and the related interrupt control bit are set to ²1² (if the stack is not full). To return from the interrupt subroutine, ²RET² or ²RETI² may be invoked. RETI will set the EMI bit to enable an in- terrupt service, but RET will not. Bit No. Label Function 0 EMI Controls the master (global) interrupt (1= enabled; 0= disabled) 1 EUI Controls the USB interrupt (1= enabled; 0= disabled) 2 ET0I Controls the Timer/Event Counter 0 interrupt (1= enabled; 0= disabled) 3 ET1I Controls the Timer/Event Counter 1 interrupt (1= enabled; 0= disabled) 4 USBF USB interrupt request flag (1= active; 0= inactive) 5 T0F Internal Timer/Event Counter 0 request flag (1= active; 0= inactive) 6 T1F Internal Timer/Event Counter 1 request flag (1= active; 0= inactive) 7 ¾ Unused bit, read as ²0² INTC (0BH) Register |
同様の部品番号 - HT82K95E_14 |
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同様の説明 - HT82K95E_14 |
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