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HT82M9BE データシート(PDF) 15 Page - Holtek Semiconductor Inc

部品番号 HT82M9BE
部品情報  USB Mouse Encoder 8-Bit MCU
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メーカー  HOLTEK [Holtek Semiconductor Inc]
ホームページ  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT82M9BE データシート(HTML) 15 Page - Holtek Semiconductor Inc

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HT82M9BE/HT82M9BA
Rev. 1.80
15
December 22, 2008
operate until overflow occurs (a Timer/Event Counter 0/1
reloading will occur at the same time). When the
Timer/Event Counter 0/1 (reading TMR0/TMR1) is read,
the clock will be blocked to avoid errors. As clock blocking
may results in a counting error, this must be taken into
consideration by the programmer.
Input/Output Ports
There are 20 bidirectional input/output lines in the
microcontroller, labeled from PA to PC, which are
mapped to the data memory of [12H], [14H] and [16H]
respectively. All of these I/O ports can be used for input
and output operations. For input operation, these ports
are non-latching, that is, the inputs must be ready at the
T2 rising edge of instruction
²MOV A,[m]² (m=12H, 14H
or 16H). For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC and
PCC) to control the input/output configuration. With this
control register, CMOS/NMOS/PMOS output or Schmitt
trigger input with or without pull-high/low resistor struc-
tures can be reconfigured dynamically under software
control. To function as an input, the corresponding latch
of the control register must write a
²1². The input source
V D D
M
U
X
P A , P B 4 , P B 7 W a k e - u p O p t i o n
R e a d D a t a R e g i s t e r
D
Q
C K
S
C o n t r o l B i t
D a t a B u s
W r i t e C o n t r o l R e g i s t e r
C h i p R e s e t
R e a d C o n t r o l R e g i s t e r
W r i t e D a t a R e g i s t e r
D a t a B i t
P u l l - l o w
P A , P B 4 , P B 7 W a k e - u p
P A 6 / T M R 0
P u l l - h i g h
P o r t O u t p u t
C o n f i g u r a t i o n
Q
P A 0 ~ P A 5 , P A 6 / T M R 0 , P A 7 / T M R 1
P B 0 ~ P B 7
P C 0 ~ P C 3
D
Q
C K
S
Q
P A 7 / T M R 1
Input/Output Ports
T M 1
T M 0
T M R 0
T E
T M 1
T M 0
T O N
P u l s e W i d t h
M e a s u r e m e n t
M o d e C o n t r o l
T i m e r / E v e n t C o u n t e r 0
P r e l o a d R e g i s t e r
T i m e r / E v e n t
C o u n t e r 0
D a t a B u s
R e l o a d
O v e r f l o w
t o I n t e r r u p t
f S Y S / 4
Timer/Event Counter 0
T M 1
T M 0
T M R 1
T E
T M 1
T M 0
T O N
P u l s e W i d t h
M e a s u r e m e n t
M o d e C o n t r o l
1 6 B i t s
T i m e r / E v e n t C o u n t e r
P r e l o a d R e g i s t e r
D a t a B u s
R e l o a d
O v e r f l o w
t o I n t e r r u p t
f S Y S / 4
1 6 B i t s
T i m e r / E v e n t C o u n t e r
( T M R 1 H / T M R 1 L )
L o w B y t e
B u f f e r
Timer/Event Counter 1


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