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SM65MLVD203D データシート(PDF) 9 Page - Texas Instruments |
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SM65MLVD203D データシート(HTML) 9 Page - Texas Instruments |
9 / 10 page SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 SLLS558A – DECEMBER 2002 – JUNE 2003 www.ti.com 9 Table 1. Type-1 Receiver Input Threshold Test Voltages APPLIED VOLTAGES RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMON– MODE INPUT VOLTAGE RECEIVER OUTPUT VIA VIB VID VIC OUTPUT 2.400 0.000 2.400 1.200 H 0.000 2.400 –2.400 1.200 L 3.800 3.750 0.050 3.775 H 3.750 3.800 –0.050 3.775 L –1.350 –1.400 0.050 –1.375 H –1.400 –1.350 –0.050 –1.375 L NOTE: H= high level, L = low level, output state assumes receiver is enabled (RE = L) Table 2. Type-2 Receiver Input Threshold Test Voltages APPLIED VOLTAGES RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMON– MODE INPUT VOLTAGE RECEIVER OUTPUT VIA VIB VID VIC OUTPUT 2.400 0.000 2.400 1.200 H 0.000 2.400 –2.400 1.200 L 3.800 3.650 0.150 3.725 H 3.800 3.750 0.050 3.775 L –1.250 –1.400 0.150 –1.325 H –1.350 –1.400 0.050 –1.375 L NOTE: H= high level, L = low level, output state assumes receiver is enabled (RE = L) 1.2 V 1.0 V tpLH 0.2 V –0.2 V VA VB VID 90% VOH VOL tpHL 10% tf tr VO VCC/2 VO VID VB VA CL 0 V 15 pF NOTES:A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 50 MHz, duty cycle = 50 ± 5%. CL is a combination of a 20%-tolerance, low-loss ceramic, surface-mount capacitor and fixture capacitance within 2 cm of the D.U.T. B. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz. Figure 10. Receiver Timing Test Circuit and Waveforms |
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