データシートサーチシステム |
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SM65MLVD207D データシート(PDF) 10 Page - Texas Instruments |
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SM65MLVD207D データシート(HTML) 10 Page - Texas Instruments |
10 / 10 page SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 SLLS558A – DECEMBER 2002 – JUNE 2003 www.ti.com 10 15 pF tpZL tpLZ VOL VOL +0.5 V VO RL 499 Ω _ + VTEST B A RE 1.2 V Inputs VCC 1 V VCC VCC/2 0 V VCC VCC/2 VTEST A RE R 0 V 1.4 V A tpZH tpHZ 0 V VOH –0.5 V VCC VCC/2 0 V VOH VCC/2 RE VO R Output VTEST CL NOTES:A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 500 kHz, duty cycle = 50 ± 5%. B. RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T. C. RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T. D. CL is the instrumentation and fixture capacitance within 2 cm of the DUT and ±20%. Figure 11. Receiver Enable/Disable Time Test Circuit and Waveforms |
同様の部品番号 - SM65MLVD207D |
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同様の説明 - SM65MLVD207D |
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