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AD73311L データシート(PDF) 13 Page - Analog Devices |
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AD73311L データシート(HTML) 13 Page - Analog Devices |
13 / 37 page REV. A AD73311L –12– SPORT Register Maps There are two register banks for the AD73311L: the control register bank and the data register bank. The control register bank consists of six read/write registers, each eight bits wide. Table IX shows the control register map for the AD73311L. The first two control registers, CRA and CRB, are reserved for controlling the SPORT. They hold settings for parameters such as bit rate, internal master clock rate and device count (used when more than one AD73311L is connected in cascade from a single SPORT). The other three registers; CRC, CRD and CRE are used to hold control settings for the ADC, DAC, Reference and Power Control sections of the device. Control registers are written to on the negative edge of SCLK. The data register bank consists of two 16-bit registers that are the DAC and ADC registers. Master Clock Divider The AD73311L features a programmable master clock divider that allows the user to reduce an externally available master clock, at pin MCLK, by one of the ratios 1, 2, 3, 4 or 5 to produce an internal master clock signal (DMCLK) that is used to calculate the sampling and serial clock rates. The master clock divider is programmable by setting CRB:4-6. Table V shows the division ratio corresponding to the various bit settings. The default divider ratio is divide-by-one. Table V. DMCLK (Internal) Rate Divider Settings MCD2 MCD1 MCD0 DMCLK Rate 0 0 0 MCLK 0 0 1 MCLK/2 0 1 0 MCLK/3 0 1 1 MCLK/4 1 0 0 MCLK/5 1 0 1 MCLK 1 1 0 MCLK 1 1 1 MCLK Serial Clock Rate Divider The AD73311L features a programmable serial clock divider that allows users to match the serial clock (SCLK) rate of the data to that of the DSP engine or host processor. The maximum SCLK rate available is DMCLK and the other available rates are: DMCLK/2, DMCLK/4 and DMCLK/8. The slowest rate (DMCLK/8) is the default SCLK rate. The serial clock divider Figure 9. SPORT Block Diagram is programmable by setting bits CRB:2–3. Table VI shows the serial clock rate corresponding to the various bit settings. Table VI. SCLK Rate Divider Settings SCD1 SCD0 SCLK Rate 0 0 DMCLK/8 0 1 DMCLK/4 1 0 DMCLK/2 1 1 DMCLK Sample Rate Divider The AD73311L features a programmable sample rate divider that allows users flexibility in matching the codec’s ADC and DAC sample rates to the needs of the DSP software. The maxi- mum sample rate available is DMCLK/256 which offers the lowest conversion group delay, while the other available rates are: DMCLK/512, DMCLK/1024 and DMCLK/2048. The slowest rate (DMCLK/2048) is the default sample rate. The sample rate divider is programmable by setting bits CRB:0-1. Table VII shows the sample rate corresponding to the various bit settings. Table VII. Sample Rate Divider Settings DIR1 DIR0 SCLK Rate 0 0 DMCLK/2048 0 1 DMCLK/1024 1 0 DMCLK/512 1 1 DMCLK/256 DAC Advance Register The loading of the DAC is internally synchronized with the unloading of the ADC data in each sampling interval. The default DAC load event happens one SCLK cycle before the SDOFS flag is raised by the ADC data being ready. However, this DAC load position can be advanced before this time by modifying the contents of the DAC Advance field in Control Register E (CRE:0–4). The field is five bits wide, allowing 31 increments of weight 1/(DMCLK/8); see Table VIII. In certain circumstances this can reduce the group delay when the ADC and DAC are used to process data in series. Appendix E details how the DAC advance feature can be used. NOTE: The DAC advance register should be changed before the DAC section is powered up. SERIAL PORT (SPORT) SERIAL REGISTER SCLK DIVIDER MCLK DIVIDER CONTROL REGISTER B CONTROL REGISTER A CONTROL REGISTER C CONTROL REGISTER D CONTROL REGISTER E MCLK (EXTERNAL) SE RESET SDIFS SDI DMCLK (INTERNAL) 3 8 8 8 8 8 2 SCLK SDOFS SDO SERIAL REGISTER CONTROL REGISTER F 8 |
同様の部品番号 - AD73311L_17 |
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同様の説明 - AD73311L_17 |
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