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MC100ES8111 データシート(PDF) 7 Page - Motorola, Inc

部品番号 MC100ES8111
部品情報  Low Voltage 1:10 Differential HSTL Clock Fanout Buffer
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メーカー  MOTOROLA [Motorola, Inc]
ホームページ  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MC100ES8111 データシート(HTML) 7 Page - Motorola, Inc

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Advanced Clock Drivers Device Data
Freescale Semiconductor
7
MC100ES8111
Freescale Confidential Proprietary
NDA Required / Preliminary
Power Supply Bypassing
The MC100ES8111 is a mixed analog/digital product. The
differential architecture of the MC100ES8111 supports low
noise signal operation at high frequencies. In order to
maintain its superior signal quality, all VCC pins should be
bypassed by high-frequency ceramic capacitors connected
to GND. If the spectral frequencies of the internally
generated switching noise on the supply pins cross the series
resonant point of an individual bypass capacitor, its overall
impedance begins to look inductive and thus increases with
increasing frequency. The parallel capacitor combination
shown ensures that a low impedance path to ground exists
for frequencies well above the noise bandwidth.
Figure 4. VCC, VCCO Power Supply Bypass
Output Enable/Disable Control
The MC100ES8111 enables and disables outputs
synchronously to the input clock signal. The user may enable
and disable the outputs by using the OE control regardless of
any hold and setup time constraints. Output runt pulses are
prevented in any case. Outputs are disabled in logic low state
(Qn=Low, Qn=High) without a change of the output
impedance.
Figure 5. MC100ES8111 Output Disable/Enable Timing
VCC
0.1 nF
33...100 nF
MC100ES8111
0.1 nF
33...100 nF
4
3.3 V ± 5%
1.8 V ± 0.1 V or
VCCO
1.5 V ± 0. 1V
CLKn
CLKn
OE
Qn
Qn
tPDL (OE to Qn)
50%
tPLE (OE to Qn)
Outputs Disabled


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