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MT9V023 データシート(PDF) 5 Page - ON Semiconductor |
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MT9V023 データシート(HTML) 5 Page - ON Semiconductor |
5 / 43 page MT9V023 www.onsemi.com 5 Table 3. BALL DESCRIPTIONS (continued) 52-Ball IBA Numbers Note Description Type Symbol B5 PIXCLK Output Pixel clock out. DOUT is valid on rising edge of this clock. B3 SHFT_CLKOUT_N Output Output shift CLK (differential negative). B2 SHFT_CLKOUT_P Output Output shift CLK (differential positive). A3 SER_DATAOUT_N Output Serial data out (differential negative). A2 SER_DATAOUT_P Output Serial data out (differential positive). B4, E2 VDD Supply Digital power 3.3 V. C8, F7 VAA Supply Analog power 3.3 V. B8 VAAPIX Supply Pixel power 3.3 V. A1, A4 VDDLVDS Supply Dedicated power for LVDS pads. B1, C3 LVDSGND Ground Dedicated GND for LVDS pads. C6, F3 DGND Ground Digital GND. C7, F6 AGND Ground Analog GND. E7, E8, D7, D8 NC NC No connect. 3 1. Pin H7 (RSVD) must be tied to GND. 2. Output enable (OE) tri-states signals DOUT0–DOUT9, LINE_VALID, FRAME_VALID, and PIXCLK. 3. No connect. These pins must be left floating for proper operation. Figure 3. Typical Configuration (Connection) − Parallel Output Mode SYSCLK LINE_VALID FRAME_VALID PIXCLK DOUT(9:0) STANDBY EXPOSURE RSVD S_CTRL_ADR0 S_CTRL_ADR1 LVDSGND LED_OUT ERROR SDATA SCLK RESET_BAR OE VDDLVDS AGND DGND VDD VAA VAAPIX Master Clock 0.1 F To Controller STANDBY from Controller or Digital GND Two−Wire Serial Interface VDD VAA VAAPIX To LED output μ Note: LVDS signals are to be left floating. |
同様の部品番号 - MT9V023_17 |
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同様の説明 - MT9V023_17 |
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