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MT9V032 データシート(PDF) 22 Page - ON Semiconductor |
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MT9V032 データシート(HTML) 22 Page - ON Semiconductor |
22 / 61 page MT9V032 www.onsemi.com 22 Table 8. REGISTER DESCRIPTIONS 0X09 (9) SHUTTER WIDTH 2 7:4 T3 Ratio One−half to the power of this value indicates the ratio of duration time t3, when saturation control gate is adjusted to level V3 to total integration when exposure knee point auto adjust control bit is enabled. This register is not shadowed, but any change made does not take effect until the following new frame. t3 = Total integration × (½)t3_ratio. Note: t1 = Total integration − t2 − t3. 6 N 0–15 W 8 Exposure Knee Point Auto Adjust Enable 0 = Auto adjust disabled. 1 = Auto adjust enabled. 1 N 0,1 W 9 Single Knee Enable 0 = Single knee disabled. 1 = Single knee enabled. 0 N 0,1 W 0X0B (11) TOTAL SHUTTER WIDTH 14:0 Total Shutter Width Total integration time in number of rows. This value is used only when AEC is disabled only (bit 0 of Register 175). This register is not shadowed, but any change made does not take effect until the following new frame. 1E0 (480) N 1–32767 W 0X0C (12) RESET 0 Soft Reset Setting this bit causes the sensor to abandon the current frame by resetting all digital logic except two−wire serial interface configuration. This is a self−resetting register bit and should always read “0.” (This bit de−asserts internal active LOW reset signal for 15 clock cycles.) 0 N 0, 1 W 1 Auto Block Soft Reset Setting this bit causes the sensor to reset the automatic gain and exposure control logic. This is a self−resetting register bit and should always read “0.” (This bit de−asserts internal active LOW reset signal for 15 clock cycles.) 0 Y 0, 1 W 0X0D (13) READ MODE 1:0 Row Bin 0 = Normal operation. 1 = Row bin 2. Two pixel rows are read per row output. Image size is effectively reduced by a factor of 2 vertically while data rate and pixel clock are not affected. Resulting frame rate is increased by 2. 2 = Row bin 4. Four pixel rows are read per row output. Image size is effectively reduced by a factor of 4 vertically while data rate and pixel clock are not affected. Resulting frame rate is increased by 4. 3 = Not valid. 0 Y 0, 1, 2 W 3:2 Column Bin 0 = Normal operation. 1 = Column bin 2. When set, image size is reduced by a factor of 2 horizontally. Frame rate is not affected but data rate and pixel clock are reduced by one−half that of master clock. 2 = Column bin 4. When set, image size is reduced by a factor of 4 horizontally. Frame rate is not affected but data rate and pixel clock are reduced by one−fourth that of master clock. 3 = Not valid. 0 Y 0, 1, 2 W 4 Row Flip Read out rows from bottom to top (upside down). When set, row readout starts from row (Row Start + Window Height) and continues down to (Row Start + 1). When clear, readout starts at Row Start and continues to (Row Start + Window Height − 1). This ensures that the starting color is main- tained. 0 Y 0, 1 W |
同様の部品番号 - MT9V032_17 |
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同様の説明 - MT9V032_17 |
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