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CD74HCT40103MT データシート(PDF) 8 Page - Texas Instruments |
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CD74HCT40103MT データシート(HTML) 8 Page - Texas Instruments |
8 / 14 page 8 Test Circuits and Waveforms FIGURE 2. FIGURE 3. FIGURE 4. FIGURE 5. FIGURE 6. FIGURE 7. NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 8. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 9. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH tr CP TC tTHL tPHL tW 90% 10% tf VS GND tPLH tTLH INPUT LEVEL 1/fMAX VS 90% 10% INPUT LEVEL GND VS MR CP tREM tW VS GND INPUT LEVEL tf 10% 90% TE tPHL TC tTHL tTLH VS tPLH VS tf INPUT LEVEL 10% 90% MR CP VS tSU VS th INPUT LEVEL GND INPUT LEVEL GND INPUTS P0 - P7 PE CP VS VS VALID tSU th VS tREC INPUT LEVEL GND INPUT LEVEL GND INPUT LEVEL GND th tSU TE OR PE CP VS tSU VS th INPUT LEVEL GND INPUT LEVEL GND CLOCK 90% 50% 10% GND VCC trCL tfCL 50% 50% tWL tWH 10% tWL + tWH = fCL I CLOCK 2.7V 1.3V 0.3V GND 3V trCL = 6ns tfCL = 6ns 1.3V 1.3V tWL tWH 0.3V tWL + tWH = fCL I CD54HC40103, CD74HC40103, CD74HCT40103 |
同様の部品番号 - CD74HCT40103MT |
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同様の説明 - CD74HCT40103MT |
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