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LMZM33602RLRR データシート(PDF) 3 Page - Texas Instruments

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部品番号 LMZM33602RLRR
部品情報  4-V to 36-V Input, 2-A Step-Down DC-DC Power Module in QFN Package
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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LMZM33602RLRR データシート(HTML) 3 Page - Texas Instruments

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1
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3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
AGND
EN/SYNC
RT
VIN
PGND
VOUT
VOUT
SW
SW
DNC
DNC
PGND
PGND
3
LMZM33602
www.ti.com
SNVSAO4 – DECEMBER 2017
Product Folder Links: LMZM33602
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
5 Pin Configuration and Functions
RLR Package
18-Pin QFN
Top View
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
1
AGND
G
Analog ground. Zero voltage reference for internal references and logic. Do not connect this pin to
PGND; the connection is made internal to the device. See the Layout section of the datasheet for a
recommended layout.
2
EN/SYNC
I
EN - Enable input to regulator. High = On, Low = Off. Can be connected to VIN. Do not float. This
pin can be used to set the input under voltage lockout with two resistors. See the Programmable
Undervoltage Lockout (UVLO) section.
SYNC - The internal oscillator can be synchronized to an external clock via AC-coupling. See the
Synchronization (SYNC) section for details.
3
RT
I
An external timing resistor connected between this pin and AGND adjusts the switching frequency of
the device. If left open, the default switching frequency is 400 kHz.
4
VIN
I
Input supply voltage. Connect external input capacitors between this pin and PGND.
5, 14, 15, 18
PGND
G
Power ground. This is the return current path for the power stage of the device. Connect pin 5 to the
input source, the load, and to the bypass capacitors associated with VIN and VOUT using power
ground planes on the PCB. Pins 14 and 15 are not connected to PGND internal to the device
and must be connected to PGND at pad 18. Connect pad 18 to the power ground planes using
multiple vias for good thermal performance. See the Layout section of the datasheet for a
recommended layout.
6, 7, 8
VOUT
O
Output voltage. These pins are connected to the internal output inductor. Connect these pins to the
output load and connect external bypass capacitors between these pins and PGND.
9, 10, 11
SW
O
Switch node. Connect these pins to a small copper island under the device for thermal relief. Do not
place any external component on these pins or tie them to a pin of another function.
12, 13
DNC
Do not connect. Each pin must be soldered to an isolated pad. These pins connect to internal
circuitry. Do not connect these pins to one another, AGND, PGND, or any other voltage.
16
FB
I
Feedback input. Connect the center point of the feedback resistor divider to this pin. Connect the
upper resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the
lower resistor (RFBB) of the feedback divider to AGND.
17
PGOOD
O
Open drain output for power-good flag. Use a 10-kΩ to 100-kΩ pullup resistor to logic rail or other
DC voltage no higher than 12 V.


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