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LF6197 データシート(PDF) 7 Page - National Semiconductor (TI) |
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LF6197 データシート(HTML) 7 Page - National Semiconductor (TI) |
7 / 12 page Test Circuit TLH11381 – 4 FIGURE 1 Circuit configuration for the measurement of feedthrough attenuation Input is connected to ground in sample mode and is connected to 20 VPP 100 kHz sine wave in hold mode Pin Descriptions Va (12) This is the positive power supply pin A a 5V to a15V supply voltage should be applied to this pin and bypassed to ground with a 01 mF ceramic capacitor in parallel with a 47 mF tantalum capaci- tor Vb (4) This is the negative power supply pin A b 5V to b15V supply voltage should be applied to this pin and bypassed to ground with a 01 mF ceramic capacitor in parallel with a 47 mF tantalum capaci- tor GND (9) This is the ground reference pin All sig- nals are referenced to the potential at this pin b Input (1) This is the inverting input of the ‘‘sam- ple’’ amplifier Connecting this pin through a resistor to the output will con- figure the sample-and-hold amplifier for unity gain Other inverting and non-in- verting gains can be set by applying the familiar op amp feedback topologies For stability reasons stray capacitance from the inverting input to ground should be minimized a Input (2) This is the non-inverting input of the ‘‘sample’’ amplifier This pin should be driven from a low impedance source Output (5) This is the output of the sample-and- hold amplifier LR1 (10) This is the Logic Reference 1 input By applying the appropriate logic threshold at this pin the sample-and-hold amplifi- er’s logic input can be made either CMOS or ECL compatible For TTL logic levels this pin should remain unconnected LR2 (13) This is the Logic Reference 2 input For TTL logic levels this pin should be con- nected to ground this sets the logic threshold at the logic comparator’s invert- ing pin at 14V For CMOS or ECL logic levels this pin should either remain un- connected or connected to pin 10 Logic Input (11) This is the logic control input pin A logic low at this pin will configure the amplifier in the ‘‘sample’’ mode while a logic high will configure the amplifier in the ‘‘hold’’ mode The TTL CMOS or ECL logic compatibility will be determined by the voltage threshold set at the logic compar- ator’s inverting input Zener Reference For optimum acquisition and settling Output (14) times this pin must be bypassed to ground with a 001 mF capacitor Further- more for g5V supply operation this pin must be biased at 25V from a low imped- ance source NC (3678) No connection 7 |
同様の部品番号 - LF6197 |
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同様の説明 - LF6197 |
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