SLG46127 datasheet(40/88 Pages) DIALOG

部品番号	SLG46127

部品情報	GreenPAK Programmable Mixed-signal Matrix

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000-0046127-101

Page 39 of 87

SLG46127

10.4.2 4-Bit LUT or 8-Bit Counter / Delay Macrocells Used as 8-Bit Counter / Delay Register Settings

Table 32. CNT/DLY2 Register Settings

Signal Function

Register Bit

Address

Register Definition

Counter/delay2

Mode Selection

reg <285>

0: Delay Mode

1: Counter Mode

Counter/delay2

Clock Source Select

reg <288:286>

000: Internal OSC Clock

001: OSC/4

010: OSC/12

011: OSC/24

100: OSC/64

101: External Clock

110: External Clock

111: Counter1 Overflow

Counter/delay2

Control Data

reg <296:289>

1 – 255 (delay time = (counter control data +2) /freq)

Delay2 Mode Select

or asynchronous

counter reset

reg <298:297>

00: Delay on both falling and rising edges(for delay & counter reset)

01: Delay on falling edge only (for delay & counter reset Delay)

10: Delay on rising edge only (for delay & counter reset)

11: No delay on either falling or rising edges / high level reset for counter mode

LUT4_0 or Count-

er2 select

reg <301>

0: LUT4_0

1: Counter2

同様の部品番号 - SLG46127

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	SLG46127MTR	8Mb / 94P	Programmable Mixed-signal Matrix with Dual 44 mΩ / 2 A P-FET Revised March 4, 2022

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