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SLG46200 データシート(PDF) 29 Page - Dialog Semiconductor |
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SLG46200 データシート(HTML) 29 Page - Dialog Semiconductor |
29 / 69 page 000-0046200-124 Page 24 of 64 SLG46200 11.6 ADC Reference Voltage The ADC’s reference voltage (VREF) is from a 3-input mux that is controlled by the 2-bit ADC_Vref_sel signal (reg <342:341>). The three reference voltage inputs are chosen from the following: •VBG of 1.796V from Internal Source • External User Defined Voltage Source (PIN 8) • Power Divider of 0.547 * VDD 11.7 ADC Power Down Mode The ADC’s power down is controlled by the connection matrix output 3 where a value of “1” will drive the ADC and the PGA to power down mode. 11.8 ADC Clock Source The ADC clock source comes from either the internal RC oscilator (CLK4ADC/64) or an external clock from PIN 4. The selection is made from the ADC_clk_sel signal via reg <340> where: • The RC Oscillator is used when the ADC_clk_select is “0” • An external clock from PIN 4 is used when the ADC_clk_sel is “1” The ADC requires 16 clock cycles to sample the analog voltage and output the sampled data. When the internal RC Oscillator is used for providing timing to the ADC, a total of 1024 clock cycles are needed since the CLK4ADC signal is also divided by 64. Figure 11. ADC Reference Voltage Bandgap (1.796V) External Vref (PIN 8) Power divider (VDD *0.0547) 10 00 01 reg <342:341> VREF Table 10. ADC Reference Voltage. reg <342:341> VREF 00 Bandgap (1.796V) 01 External (PIN 8) 10 Power Divider (0.547 * VDD) 11 N/A Figure 12. ADC Clock Source 1 0 EXT. CLK (PIN 4) CLK4ADC/64 reg <340> CLK |
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同様の説明 - SLG46200 |
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