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TSB15LV01IPFC データシート(PDF) 11 Page - Texas Instruments |
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TSB15LV01IPFC データシート(HTML) 11 Page - Texas Instruments |
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11 / 74 page  1–5 1.4 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION Analog Front End (AFE) Interface ADCLK 13 O ADC clock. Triggers the AFE’s analog/digital converter to sample the amplifier output, and clocks the digital data out of the AFE to the TSB15LV01. CLAMP 2 O Pulse that instructs AFE to electrically clamp the ac-coupled pixel pulse to a fixed reference voltage. OBCLP 6 O Optical Black Clamp pulse. Instructs the AFE to clamp its ADC output to a digital black reference value. Samples occur during the black pixel portion of the CCD’s image signal. PIXEL_DATA9– PIXEL_DATA0 15 – 19, 22 – 26 I Data bus that inputs processed video data from the AFE’s analog/digital converter. PIXEL_DATA_IN9 is the MSB of these 10 bits. SERIAL _CS 8 O Serial interface chip select. Allows programming of AFE control registers. Signifies the beginning of data transmission on SERIAL_DATA. SERIAL _DATA 9 O Serial interface digital data input. Allows programming of AFE control registers. SERIAL _CLK 10 O Serial interface clock. Allows programming of AFE control registers. Clocks data out of SERIAL_DATA. SR 4 O CCD reset-pedestal sampling pulse. Triggers the AFE to sample the reset pedestal of the pixel pulse received from the CCD image sensor. SV 3 O CCD video data sampling pulse. Triggers the AFE to sample the data pedestal of the pixel pulse received from the CCD image sensor. CCD Interface ABD_XSUB 35 O Image area clear bias. Goes high to clear the image area. This pulse performs an electronic shutter function, controlling the integration time of the CCD image. Performed at the beginning of every frame. ABSP_XSG 32 O Antiblack smear. Goes low to increase the pixel well size during parallel transfer. H2 37 O Horizontal transfer 2. Horizontal charge transfer control for CCD. IAG_XV3 29 O Image-area gate/vertical transfer 3. Charge transfer control for CCD. RST_RG 39 O Reset gate. Reset pulse for the CCD’s charge-detection amplifier, generated for every pixel moved out of the CCD. SAG_XV1 34 O Storage-area gate/vertical transfer 1. Charge transfer control for CCD. SRG_H1 38 O Serial register gate/horizontal transfer 1. Horizontal charge transfer control for CCD. XV2 33 O Vertical transfer 2. Charge transfer control for CCD. PHY Interface CTL1, CTL0 55 56 I/O Control 1 and control 0 of the PHY-link control bus. D[7..0] 45 – 48, 50 – 53 I/O Data signals of the PHY-link data bus. Data is expected on D0-D1 at 100 Mbits/s, D0-D3 at 200 Mbits/s, and D0-D7 at 400 Mbits/s. D0 is the MSB. LREQ 60 I/O Makes bus requests and accesses to the PHY. RESET 62 I Reset, active low. The asynchronous reset to the link controller. SCLK 58 I System clock. SCLK is a 49.152-MHz clock supplied by the PHY. EEPROM Interface EEPROM_CS 66 O EEPROM chip select. EEPROM_SCLK 64 O EEPROM serial data clock. EEPROM_SI 65 O EEPROM serial data output. EEPROM_SO 68 I EEPROM serial data input. |
同様の部品番号 - TSB15LV01IPFC |
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同様の説明 - TSB15LV01IPFC |
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