MPEG-4 Video Decoder LSI

Preliminary

TC35274

TOSHIBA Confidential

2000-4-27

8/13

Version 0.90

Fig. 4 Write Operation in handshake mode

3.1.2 Synchronized access mode

In this mode, a host CPU accomplishs an access to TC35274 in the specified period without a

handshake. However, if the host CPU accesses to the embedded DRAM in TC35274, it has to check

whether the next access is available or not by checking a status register at every 8 accesses.

Fig.5 shows the timing diagram of a read operation. A read access starts by asserting both a chip

select signal (/HCS) and a read signal (/RD) (timing (a)). After the specified cycles indicated as Tacs,

the host CPU gets the read data and finishes the read operation by negating both /HCS and /HRD

(timing (b)).

Fig.6 shows the timing diagram of a write operation. A write access starts by asserting both /HCS

and a write signal (/WR) (timing (a)). After the specified cycles, the host CPU finishes the write

operation by negating both /HCS and /HWR (timing (b)).

HADDR

/HWR

HDAT

/HWAIT

/HCS

T

CSS

T

WTAD

T

DTWS

T

DTID

T

RDH

T

RR

T

ADH

T

WTID

T

ADS

T

CSH

(a)

(b)

(c)