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Issue 0

LANSDALE Semiconductor, Inc.

ML145162

Figure 12. Programming Format for Control Register (3–Pin Interfacing Scheme)

AUX DATA SELECT = 0

ENB

CONTROL REGISTER IDENTIFIER = 1

REF PD

ENABLE

RxPD

ENABLE

TxPD

ENABLE

10

TEST

BIT

AUX

DATA

SELECT

CONTROL REGISTER DATA

Din

REF

OUT

MSB

LSB

CLK

NOTE: ENB must be high during the serial transfer.

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16–BIT Rx COUNTER

DIVIDE RATIO

Din

ENB

16–BIT Tx COUNTER

DIVIDE RATIO

Figure 13. Programming Format for Transmit and Receive Counters

(3–Pin Interfacing Scheme)

CLK

NOTE: ENB must be low during the serial transfer.

LAST

CLOCK

CONTROL REGISTER IDENTIFIER = 1

REF PD

ENABLE

RxPD

ENABLE

TxPD

ENABLE

AUX

DATA

SELECT

REF

OUT

1

Din

ENB

CONTROL REGISTER DATA

AUX DATA SELECT = 1

MSB

LSB

Figure 14. Programming Format for Control Register (4–Pin Interfacing Scheme)

CLK

NOTE: ENB must be high during the serial transfer.

0

TEST

BIT

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