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MC145157P2 データシート(PDF) 6 Page - LANSDALE Semiconductor Inc.

部品番号 MC145157P2
部品情報  PLL Frequency Synthesizer Family
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メーカー  LANSDALE [LANSDALE Semiconductor Inc.]
ホームページ  http://www.lansdale.com
Logo LANSDALE - LANSDALE Semiconductor Inc.

MC145157P2 データシート(HTML) 6 Page - LANSDALE Semiconductor Inc.

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Page 6 of 35
Issue A
LANSDALE Semiconductor, Inc.
ML145152
12 x 8 ROM REFERENCE DECODER
φV
ML145152 BLOCK DIAGRAM
φR
12–BIT
÷ R COUNTER
PHASE
DETECTOR
LOCK
DETECT
LD
fin
OSCin
OSCout
12
N0
N2
N4 N5
N7
N9
NOTE: N0 – N9, A0 – A5, and RA0 – RA2 have pull–up resistors that are not shown.
10–BIT
÷ N COUNTER
CONTROL
LOGIC
MC
6–BIT
÷ A COUNTER
A5
A3 A2
A0
RA2
RA0
RA1
PIN DESCRIPTIONS
INPUT PINS
fin
Frequency Input (Pin 1)
Input to the positive edge triggered ÷ N and ÷ A counters.
fin is typically derived from a dual–modulus prescaler and is
AC coupled into the device. For larger amplitude signals (stan-
dard CMOS logic levels) DC coupling may be used.
RA0, RA1, RA2
Reference Address Inputs (Pins 4, 5, 6)
These three inputs establish a code defining one of eight
possible divide values for the total reference divider. The total
reference divide values are as follows:
N0 – N9
N Counter Programming Inputs (Pins 11 – 20)
The N inputs provide the data that is preset into the ÷ N
counter when it reaches the count of 0. N0 is the least signifi-
cant digit and N9 is the most significant. Pull–up resistors en-
sure that inputs left open remain at a logic 1 and require only a
SPST switch to alter data to the zero state.
A0 – A5
A Counter Programming Inputs(Pins 23, 21, 22, 24, 25, 10)
The A inputs define the number of clock cycles of fin that
require a logic 0 on the MC output (see Dual–Modulus Pres-
caling section). The A inputs all have internal pull–up resis-
tors that ensure that inputs left open will remain at a logic 1.
OSCin, OSCout
Reference Oscillator Input/Output (Pins 27, 26)
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be con-
nected from OSCin to ground and OSCout to ground. OSCin
may also serve as the input for an externally generated refer-
ence signal. This signal is typically AC coupled to OSCin, but
for larger amplitude signals (standard CMOS logic levels) DC
coupling may also be used. In the external reference mode, no
connection is required to OSCout.
OUTPUT PINS
φR,φV
Phase Detector B Outputs (Pins 7, 8)
These phase detector outputs can be combined externally for
a loop–error signal.
If the frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by φV pulsing low.
φR remains essentially high.
If the frequency fV is less than fR or if the phase of fV is
lagging, then error information is provided by φR pulsing low.
φV remains essentially high.
If the frequency of fV = fR and both are in phase, then both
φV and φR remain high except for a small minimum time peri-
od when both pulse low in phase.
MC
Dual–Modulus Prescale Control Output (Pin 9)
Signal generated by the on–chip control logic circuitry for
controlling an external dual–modulus prescaler. The MC level
will be low at the beginning of a count cycle and will remain
low until the ÷ A counter has counted down from its pro-
grammed value. At this time, MC goes high and remains high
until the ÷ N counter has counted the rest of the way down
from its programmed value (N – A additional counts since
both ÷ N and ÷ A are counting down during the first portion of
the cycle). MC is then set back low, the counters preset to
Reference Address Code
Total
Divide
RA2
RA1
RA0
Divide
Value
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
64
128
256
512
1024
1160
2048


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