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CS1611 データシート(PDF) 11 Page - Cirrus Logic

部品番号 CS1611
部品情報  TRIAC Dimmable LED Driver IC
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メーカー  CIRRUS [Cirrus Logic]
ホームページ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS1611 データシート(HTML) 11 Page - Cirrus Logic

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CS1610/11/12/13
DS929F3
11
A quasi-resonant buck stage is illustrated in Figure 13. The
buck stage is controlled by measuring current in the buck
inductor and voltage on the auxiliary winding.
Figure 13. Buck Model
The digital buck algorithm ensures monotonic dimming from
2% to 100% of the dimming range with a linear relationship
between the dimming signal and the LED current.
Quasi-resonant operation is achieved by detecting second
stage inductor demagnetization via an auxiliary winding. The
digital control algorithm rejects line-frequency ripple created
on the second stage input by the front-end boost stage,
resulting in the highest possible LED efficiency and long LED
life.
5.7.1
Auxiliary Winding Configuration
The auxiliary winding is also used for zero-current
detection (ZCD) and overvoltage protection (OVP). The
auxiliary winding is sensed through the FBAUX pin of the IC.
5.7.2
Control Parameters
The second stage control parameters assure:
• Line Regulation — The LED current remains constant
despite a ±10% AC line voltage variation.
• Effect of Variation in Transformer Magnetizing
Inductance
— The LED current remains constant over
a ±20% variation in magnetizing inductance.
The second stage requires three inputs and generates one
key output. The FBSENSE input is used to sense the current
in the second stage inductor. When the current reaches a
certain threshold, the gate drive turns off (output on pin GD).
The sensed current and the FBGAIN input are used to
determine the switching period Ttotal. The zero-current detect
input on pin FBAUX is used to determine the demagnetization
period T2. The controller then uses the time Ttotal to determine
gate turn-on time.
The FBGAIN input is set using an external resistor, RFBGAIN.
Resistor RFBGAIN must be selected to ensure that the
switching period Ttotal is greater than the resonant switching
period Tcritical at maximum output power. See Equation 5:
where,
Tcritical = resonant switching period at max power
T1 = gate turn-on time
T2 = demagnetization time
The switching period Ttotal is computed using the formula
shown in Equation 6:
where,
= dimming factor, proportional to the duty cycle of the
dimmer, between 0 and 1
IPK(FB) = transformer primary winding current
FBgain =Ttotal/T2
An appropriate value for RFBGAIN needs to be selected to
provide the correct FBgain. Resistor RFBGAIN is calculated
using the formula shown in Equation 7:
The value of FBgain also has a bearing on the linearity of the
dimming factor versus the LED current curve and must be
chosen using Application Note AN364: CS1610/11 Design
Guide.
5.7.3
Output Open Circuit Protection
Output open circuit protection and output overvoltage
protection (OVP) is implemented by monitoring the output
voltage through the transformer auxiliary winding. If the
voltage on the FBAUX pin exceeds a threshold (VOVP(th)) of
1.25V, a fault condition occurs. The IC output is disabled and
the controller attempts to restart after one second.
5.7.4
Overcurrent Protection (OCP)
Overcurrent protection is implemented by monitoring the
voltage across the second stage sense resistor. If this voltage
exceeds a threshold (VOCP(th)) of 1.69V, a fault condition
occurs. The IC output is disabled and the controller attempts
to restart after one second.
5.7.5
Open Loop Protection (OLP)
Both open loop protection and protection against a short of the
second stage sense resistor are implemented by monitoring
the voltage across the resistor. If the voltage on pin FBSENSE
does not reach the protection threshold (VOLP(th)) of 200mV,
the IC output is disabled and the controller attempts to restart
after one second.
13
11
R
FB GA IN
FBGAIN
FBAUX
GND
GD
FBSENSE
15
9
12
CS1612/13
R12
R11
R13
Q4
LED +
LED -
VBST
C8
D8
C9
L3
Ttotal
Tcritical T1 T2
+
=

[Eq.5]
Ttotal
IPK FB

T2
FBgain
------------------
[Eq.6]
RFBGAIN
4000000
FBgain 128
 64
----------------------------------------------------
=
[Eq.7]


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