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LM12L438CIV データシート(PDF) 11 Page - National Semiconductor (TI) |
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LM12L438CIV データシート(HTML) 11 Page - National Semiconductor (TI) |
11 / 80 page 20 Electrical Specifications (Continued) 23 DIGITAL SWITCHING CHARACTERISTICS The following specifications apply to the LM12434 and LM12 L 438 for VAa e VDae 5V 33V AGND e DGND e 0V CL (load capacitance) on output lines e 80 pF unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits for TA e TJ e 25 C (Notes 6 7 and 9) (Continued) 232 8051 Interface Mode Symbol Parameter Conditions Typical Limits Units (See Figure Below) (Note 10) (Note 11) (Limit) t9 TXD (Serial Clock Period) 125 250 ns (min) t10 CS Set-Up Time to First 25 40 ns (min) Clock Transition t11 Data in Valid Set-Up Time to 40 ns (min) TXD Clock High t12 Data in Valid Hold Time 40 90 ns (min) from TXD Clock High t13 Data Out Hold Time 70 120 ns (max) from TXD Clock High t14 CS Hold Time from Last TXD High in a Read or Write Cycle 25 50 ns (min) (Excluding Burst Read Cycle) t15 CS Inactive to CS Active Again 3 CLK Cycle (min) t16 SCLK Idle Time between the End of the Command Byte 3 CLK Cycle Transfer and the Start of the (min) Data Transfer in Read Cycles CLK is the main clock input to the device pin number 24 in PLCC package or pin number 2 in SO package TLH11879 – 21 11 |
同様の部品番号 - LM12L438CIV |
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同様の説明 - LM12L438CIV |
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