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LF13509N データシート(PDF) 6 Page - National Semiconductor (TI) |
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LF13509N データシート(HTML) 6 Page - National Semiconductor (TI) |
6 / 16 page Application Hints The LF11508 series is an 8-channel analog multiplexer which allows the connection of a single load to 1 of 8 differ- ent analog inputs These multiplexers incorporate JFETs in a switch configuration which insures a constant ‘‘ON’’ resist- ance over the analog voltage range of the device Four TTL compatible inputs are provided a 3-bit binary decode to se- lect a particular channel and an enable input used as a package select The switches operate with a break-before- make action preventing the temporary connection of 2 ana- log inputs during switching Because these multiplexers are fabricated with the BI-FET process rather than CMOS they do not require special handling The LF11509 series is a 4-channel differential multiplexer which allows two loads to be connected to 1 of 4 different pairs of analog inputs The LF11509 series also has all the features of the LF11508 ANALOG VOLTAGE AND CURRENT The ‘‘ON’’ resistance RON of the analog switches is con- stant over a wide input range from positive (VCC) supply to negative (bVEE) supply The analog input should not exceed either positive or nega- tive supply without limiting the current to less than 10 mA otherwise the multiplexer may get damaged For proper op- eration however the positive analog voltage should be kept equal to or less than VCC b 4V as this will increase the switch leakage in both ‘‘ON’’ and ‘‘OFF’’ state and it may also cause a false turn ‘‘ON’’ of a normally ‘‘OFF’’ switch This limit applies over the full temperature range The maximum allowable switch ‘‘ON’’ voltage (the drop across the switch in the ‘‘ON’’ condition) is g04V over tem- perature If this number is to exceed the input current should be limited to 10 mA The ‘‘ON’’ resistance of the multiplexing switches varies slightly with analog current because they are JFETs running at 0V gate to source The JFET characteristics shown in Figure 4 indicates how RON tends to vary with current A lower RON is possible when the source voltage is negative with respect to the drain voltage because the JFET be- comes enhanced Caution should be used when operating in this mode as this may forward-bias an internal transistor and cause high currents to flow in the switches Thus the drain voltage should never be greater than 04V positive with respect to the source voltage without limiting the drain current to less than 10 mA LEAKAGE CURRENTS Leakage currents will remain within the specified value as long as the drain and source remain within the specified analog voltage range As the switch terminals exceed the positive analog voltage range ‘‘ON’’ and ‘‘OFF’’ leakage currents increase The ‘‘ON’’ leakage increases due to an internal clamp required by the switch structure The ‘‘OFF’’ leakage increases because the gate to source reverse bias has been decreased to the point where the switch becomes active Leakage currents vary slightly with analog voltage and will approximately double for every 10 C rise in temper- ature SWITCHING TIMES AND TRANSIENTS These multiplexers operate with a break-before-make switch action The turn off time is much faster than the turn on time to guarantee this feature over the full range of ana- log input voltage and temperature Switching transients are introduced when a switch is turned ‘‘OFF’’ The amplitude of these transients may be reduced by increasing the load ca- pacitance or decreasing the load resistance The actual charge transfer in the transient may be reduced by operat- ing on reduced power supplies Examples of switching times and transients are shown in the typical characteristic curves The enable function switching times are specified separately from switch-to-switch transition times and may be thought of as package-to-package transition times LOGIC INPUTS AND ENABLE INPUT Switch selection in the LF11508 series is accomplished by using a 3-bit binary decode while the LF11509 series uses a 2-bit decode These binary logic inputs are compatible with both TTL and CMOS logic voltage levels The maximum positive voltage applied to these inputs may exceed VCC but should not exceed bVEEa36V The maximum negative voltage should not be less than 4V below ground as this will cause an internal device to zener and all the switches will turn ‘‘ON’’ As shown in the schematic diagram the logic low bias cur- rent will flow until the PNP input is raised above the 3 diode reference ( 21V) Above this voltage the input device be- comes reverse biased and the input current drops to the leakage of the reverse biased junction (k01 mA) TLH5668 – 12 FIGURE 4 JFET Characteristics 6 |
同様の部品番号 - LF13509N |
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同様の説明 - LF13509N |
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