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TLV75519PDQNT データシート(PDF) 3 Page - Texas Instruments |
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TLV75519PDQNT データシート(HTML) 3 Page - Texas Instruments |
3 / 30 page 1 OUT 6 IN 2 NC 5 NC 3 GND 4 EN Not to scale Thermal Pad 1 IN 2 GND 3 EN 4 NC 5 OUT Not to scale 1 OUT 2 GND 5 3 EN 4 IN Not to scale 3 TLV755P www.ti.com SBVS320 – NOVEMBER 2017 Product Folder Links: TLV755P Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 5 Pin Configuration and Functions DQN Package 6-Pin X2SON Top View DBV Package 5-Pin SOT-23 Top View DRV Package 6-Pin WSON With Exposed Thermal Pad Top View NC = no internal connection. (1) The nominal input and output capacitance must be greater than 0.47 µF; throughout this document the nominal derating on these capacitors is 50%. Take care to ensure that the effective capacitance at the pin is greater than 0.47 µF. Pin Functions PIN I/O DESCRIPTION NAME DQN DBV DRV EN 3 3 4 I Enable pin. Drive EN greater than VHI to turn on the regulator. Drive EN less than VLO to place the LDO into shutdown mode. GND 2 2 3 — Ground pin. IN 4 1 6 I Input pin. A capacitor with a value of 1 µF or larger is required from this pin to ground(1). See the Input and Output Capacitor Selection section for more information. NC — 4 2, 5 — No internal connection. OUT 1 5 1 O Regulated output voltage pin. A capacitor with a value of 1 µF or larger is required from this pin to ground(1). See the Input and Output Capacitor Selection section for more information. Thermal pad — — Pad — Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND. |
同様の部品番号 - TLV75519PDQNT |
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同様の説明 - TLV75519PDQNT |
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