PAC5255_18 datasheet(44/74 Pages) ACTIVE-SEMI

部品番号	PAC5255

部品情報	Power Application Controller

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メーカー	ACTIVE-SEMI [Active-Semi, Inc]

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PAC5255

Power Application Controller

signal from the CAFE can be used to disable low-side group 1, high-side group 1, or both depending on the PR1 mask bit

settings. The PR2 signal from the CAFE can be used to disable low-side group 2, high-side group 2, or both depending on

the PR2 mask bit settings. ENHS2 (high-side group 2 control output) pin is provided for enabling external power drivers

with fault protection.

12.3.7. Low-Speed Clock Output

The ASPD incorporates an option for a low-speed clock output. This is primarily for applications which need to measure an

internally generated clock, to compare it to the main clock (such as IEC 60730 Class B Safety). By default, the

CLKOUT/ENHS2 pin will generate a 290Hz 5V square wave clock, but this pin can be configured to change the clock

frequency (290Hz, 580Hz or 1.16kHz), or select between output clock and ENHS2 (high-side group 2 control output – as

described above).

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Rev 1.10‒March 3, 2018

同様の部品番号 - PAC5255_18

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