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S29GL512N データシート(PDF) 46 Page - Cypress Semiconductor

部品番号 S29GL512N
部品情報  512, 256, 128 Mbit, 3 V, Page Flash Featuring 110 nm MirrorBit
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メーカー  CYPRESS [Cypress Semiconductor]
ホームページ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

S29GL512N データシート(HTML) 46 Page - Cypress Semiconductor

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Document Number: 002-01522 Rev. *B
Page 46 of 92
S29GL512N
S29GL256N
S29GL128N
to indicate the operation was successful. However, a succeeding read shows that the data is still 0. Only erase operations can
convert a 0 to a 1.
9.5.3
Accelerated Program
The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin,
the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program
command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC
pin must not be at VHH for operations other than accelerated programming, or device damage may result. WP# has an internal pull-
up; when unconnected, WP# is at VIH.
Figure 9.2 on page 48 illustrates the algorithm for the program operation. Refer to Erase and Program Operations on page 71 for
parameters, and Figure 15.4 on page 72 for timing diagrams.


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