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S29GL512N データシート(PDF) 71 Page - Cypress Semiconductor

部品番号 S29GL512N
部品情報  512, 256, 128 Mbit, 3 V, Page Flash Featuring 110 nm MirrorBit
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メーカー  CYPRESS [Cypress Semiconductor]
ホームページ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

S29GL512N データシート(HTML) 71 Page - Cypress Semiconductor

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Document Number: 002-01522 Rev. *B
Page 71 of 92
S29GL512N
S29GL256N
S29GL128N
15.3
Erase and Program Operations
Notes
1. Not 100% tested.
2. See Erase And Programming Performance on page 77 for more information.
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. Unless otherwise indicated, AC specifications for 90 ns, 100 ns, and 110 ns speed options are tested with VIO = VCC = 3 V. AC specifications for 110 ns speed options
are tested with VIO = 1.8 V and VCC = 3.0 V.
6. 90 ns speed option only applicable to S29GL128N and S29GL256N.
Parameter
Speed Options
JEDEC
Std.
Description
90
(Note 6)
100
110
110
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
90
100
110
110
ns
tAVWL
tAS
Address Setup Time
Min
0
ns
tASO
Address Setup Time to OE# low during toggle bit
polling
Min
15
ns
tWLAX
tAH
Address Hold Time
Min
45
ns
tAHT
Address Hold Time From CE# or OE# high
during toggle bit polling
Min
0
ns
tDVWH
tDS
Data Setup Time
Min
45
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tCEPH
CE# High during toggle bit polling
Min
20
tOEPH
Output Enable High during toggle bit polling
Min
20
ns
tGHWL
tGHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
35
ns
tWHDL
tWPH
Write Pulse Width High
Min
30
ns
tWHWH1 tWHWH1
Write Buffer Program Operation (Notes 2, 3)
Typ
240
µs
Effective Write Buffer Program
Operation (Notes 2, 4)
Per Word
Typ
µs
15
Accelerated Effective Write Buffer
Program Operation (Notes 2, 4)
Per Word
Typ
µs
13.5
Program Operation (Note 2)
Word
Typ
µs
60
Accelerated Programming Operation
(Note 2)
Word
Typ
µs
54
tWHWH2 tWHWH2 Sector Erase Operation (Note 2)
Typ
0.5
sec
tVHH
VHH Rise and Fall Time (Note 1)
Min
250
ns
tVCS
VCC Setup Time (Note 1)
Min
50
µs
tBUSY
Erase/Program Valid to RY/BY# Delay
Max
90
ns


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