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S29GL512N データシート(PDF) 77 Page - Cypress Semiconductor

部品番号 S29GL512N
部品情報  512, 256, 128 Mbit, 3 V, Page Flash Featuring 110 nm MirrorBit
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メーカー  CYPRESS [Cypress Semiconductor]
ホームページ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

S29GL512N データシート(HTML) 77 Page - Cypress Semiconductor

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Document Number: 002-01522 Rev. *B
Page 77 of 92
S29GL512N
S29GL256N
S29GL128N
16. Erase And Programming Performance
Notes
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 10,000 cycles, checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 3.0 V, 100,000 cycles.
3. Effective write buffer specification is based upon a 16-word write buffer operation.
4. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table on page 54 and Table on page 57
for further information on command definitions.
17. TSOP Pin and BGA Package Capacitance
Notes
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
Parameter
Typ
(Note 1)
Max
(Note 2)
Unit
Comments
Sector Erase Time
0.5
3.5
sec
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
S29GL128N
64
256
sec
S29GL256N
128
512
S29GL512N
256
1024
Total Write Buffer Programming Time (Note 3)
240
µs
Excludes system level
overhead (Note 5)
Total Accelerated Effective Write Buffer Programming
Time (Note 3)
200
µs
Chip Program Time
S29GL128N
123
sec
S29GL256N
246
S29GL512N
492
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
TSOP
6
7.5
pF
BGA
4.2
5.0
pF
COUT
Output Capacitance
VOUT = 0
TSOP
8.5
12
pF
BGA
5.4
6.5
pF
CIN2
Control Pin Capacitance
VIN = 0
TSOP
7.5
9
pF
BGA
3.9
4.7
pF


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