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ST78C36/36A

REV. 5.0.1

ECP/EPP PARALLEL PRINTER PORT WITH 16-BYTE FIFO

5

1.0

OVERVIEW

This device is designed around the Hewlett Packard/Microsoft specification for Extended Capabilities Port

Protocol with “ECR mode 100” defined as Enhanced Parallel Port (EPP) mode. The internal timing engines

were designed around a 24 MHz reference, which can be supplied from an external source or by the built-in

oscillator circuit (ST78C36ACJ and ST78C36CQ64 only) with an appropriate crystal.

At system RESET, the device defaults to standard IBM PC compatible Centronics printer mode (output only).

The bi-directional PS/2, EPP, and ECP modes can only be activated by programming the ECR mode field (this

requires address bit A10 = 1, which is outside the normal ISA I/O space).

Optional capabilities of the ECP specification are set as follows:

s

ECP defined interrupts are pulsed, LOW true (Centronics -ACK is non-pulsed, LOW true).

s

PWord size is forced to 1 byte.

s

There is 1 byte in the transmitter that does not affect the FIFO full bit (ECP modes).

s

RLE compression is not supported in hardware.

s

IRQ channel is selectable as 5, 7, or 9 (ST78C36CQ64 only).

s

DMA channel is selectable as 1, 2, or 3 (ST78C36CQ64 only).

s

FIFO THRESHOLD is set at 8 (used only for non-DMA access to the FIFO).

VCC

44

16, 56

Pwr

Power Supply (+5V).

GND

23,30

15, 25,

37, 48,

64

Pwr

Supply Ground.

PORT

ADDRESS

R/W

MODE

FUNCTION

DATA

000

R/W

000, 001

Data Register

ECP-AFIFO

000

W

011

ECP FIFO (Address)

DSR

001

R

All

Status Register

DCR

002

R/W

All

Control Register

EPP-APort

003

R/W

100

EPP Port (Address)

EPP-DPort

004 - 007

R/W

100

EPP Port (Data)

C-FIFO

400

W

010

Parallel Port Data FIFO

ECP-DFIFO

400

R/W

011

ECP FIFO (Data)

T-FIFO

400

R/W

110

Test FIFO

Cnfg-A

400

R

111

Configuration Register A

Cnfg-B

401

R/W

111

Configuration Register B

ECR

402

R/W

All

Extended Control Register

PIN DESCRIPTION

PIN

#

PIN

#