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AK4133 データシート(PDF) 17 Page - Asahi Kasei Microsystems

部品番号 AK4133
部品情報  192kHz 24bit Sample Rate Converter
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メーカー  AKM [Asahi Kasei Microsystems]
ホームページ  http://www.akm.com
Logo AKM - Asahi Kasei Microsystems

AK4133 データシート(HTML) 17 Page - Asahi Kasei Microsystems

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[AK4133]
015015325-E-02
2018/05
- 17 -
System Clock for Output PORT
The output ports work in both master mode and slave mode. In master mode, the output port is operated
with OLRCK and OBICK generated from OMCLK. OLRCK and OBICK clocks are output from the
OLRCK pin and OBICK pin, respectively. In slave mode, the output port is operated by input clocks from
the OLRCK pin and the OBICK pin. The OMCLK pin is not used in slave mode. It must be connected to
DVSS.
The CM1-0 pins select master or slave mode.
Table 3. Output PORT Master/Slave Mode Control (AK4133)
Mode
CM1 pin
CM0 pin
Master / Slave
OMCLK Frequency
0
L
L
Master
256FSO
1
L
H
Slave
Not used. (* 17)
2
H
L
Master
512FSO
3
H
H
Master
128FSO
Note:
* 17. The OMCLK pin must be connected to DVSS in slave mode.
Audio Interface Format of the Output Port
The ODIF pin controls the audio interface mode of the output port. The data format is MSB first in 2
’s
complement. The data is output on a falling edge of OBICK from the SDTO pin. The audio interface
format of the output port should be changed while the PDN pin =
“L”.
Table 4. Output PORT Audio Interface Format
Mode
ODIF pin
SDTO Format
OBICK (Slave)
OBICK (Master)
0
L
MSB justified
 48fs or 32fs
64fs
1
H
I
2S Compatible
 48fs or 32fs
64fs
OLRCK
OBICK(64fs)
SDTO(O)
0
1
2
15
16
19
23
24
31
0
1
2
15
16
19
23
24
31
0
1
23
23 22
19
18
18
4
23: MSB, 0:LSB @ 24-bit
0
Lch Data
Rch Data
0
4
20
20
19
22
4
Figure 13. Mode 0 MSB Justified Timing
OLRCK
OBICK(64fs)
SDTO(O)
0
1
2
15
16
19
24
25
31
0
1
2
15
16
19
24
25
31
0
1
23
20
19
19
5
23: MSB, 0:LSB @ 24-bit
0
Lch Data
Rch Data
0
5
20
20
20
23
Figure 14. Mode1 I
2S Compatible Timing


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