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FAN3100C データシート(PDF) 14 Page - ON Semiconductor |
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FAN3100C データシート(HTML) 14 Page - ON Semiconductor |
14 / 21 page www.onsemi.com 14 Applications Information Input Thresholds The FAN3100 offers TTL or CMOS input thresholds. In the FAN3100T, the input thresholds meet industry-standard TTL logic thresholds, independent of the VDD voltage, and there is a hysteresis voltage of approximately 0.4 V. These levels permit the inputs to be driven from a range of input logic signal levels for w hich a voltage over 2 V is considered logic HIGH. The driving signal for the TTL inputs should have fast rising and falling edges w ith a slew rate of 6 V/µs or faster, so the rise time from 0 to 3.3 V should be 550 ns or less. With reduced slew rate, circuit noise could cause the driver input voltage to exceed the hysteresis voltage and retrigger the driver input, causing erratic operation. In the FAN3100C, the logic input thresholds are dependent on the VDD level and, w ith VDD of 12 V, the logic rising edge threshold is approximately 55% of VDD and the input falling edge threshold is approximately 38% of VDD. The CMOS input configuration offers a hysteresis voltage of approximately 17% of VDD. The CMOS inputs can be used w ith relatively slow edges (approaching DC) if good decoupling and bypass techniques are incorporated in the system design to prevent noise from violating the input voltage hysteresis w indow . This allow s setting precise timing intervals by fitting an R-C circuit betw een the controlling signal and the IN pin of the driver. The slow rising edge at the IN pin of the driver introduces a delay betw een the controlling signal and the OUT pin of the driver. Static Supply Current In the IDD (static) typical performance graphs (Figure 9 - Figure 10 and Figure 15 - Figure 16), the curve is produced w ith all inputs floating (OUT is LOW) and indicates the low est static IDD current for the tested configuration. For other states, additional current flow s through the 100 k Ω resistors on the inputs and outputs show n in the block diagrams (see Figure 5 - Figure 6). In these cases, the actual static IDD current is the value obtained from the curves plus this additional current. M illerDrive™ Gate Drive Technology FAN3100 drivers incorporate the MillerDrive™ architecture show n in Figure 42 for the output stage, a combination of bipolar and MOS devices capable of providing large currents over a w ide range of supply voltage and temperature variations. The bipolar devices carry the bulk of the current as OUT sw ings betw een 1/3 to 2/3 VDD and the MOS devices pull the output to the high or low rail. The purpose of the MillerDrive™ architecture is to speed up sw itching by providing the highest current during the Miller plateau region w hen the gate-drain capacitance of the MOSFET is being charged or discharged as part of the turn-on / turn-off process. For applications that have zero voltage sw itching during the MOSFET turn-on or turn-off interval, the driver supplies high peak current for fast sw itching even though the Miller plateau is not present. This situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the MOSFET is sw itched on. The output pin slew rate is determined by VDD voltage and the load on the output. It is not user adjustable, but if a slow er rise or fall time at the MOSFET gate is needed, a series resistor can be added. Input stage V DD V OUT Figure 42. MillerDrive™ Output Architecture Under-Voltage Lockout The FAN3100 start-up logic is optimized to drive ground referenced N-channel MOSFETs w ith a under-voltage lockout (UVLO) function to ensure that the IC starts up in an orderly fashion. When VDD is rising, yet below the 3.9 V operational level, this circuit holds the output LOW, regardless of the status of the input pins. After the part is active, the supply voltage must drop 0.2 V before the part shuts dow n. This hysteresis helps prevent chatter w hen low VDD supply voltages have noise from the pow er sw itching. This configuration is not suitable for driving high-side P-channel MOSFETs because the low output voltage of the driver w ould turn the P-channel MOSFET on w ith VDD below 3.9 V. VDD Bypass Capacitor Guidelines To enable this IC to turn a pow er device on quickly, a local, high-frequency, bypass capacitor CBYP w ith low ESR and ESL should be connected betw een the VDD and GND pins w ith minimal trace length. This capacitor is in addition to bulk electrolytic capacitance of 10µF to 47µF often found on driver and controller bias circuits. A typical criterion for choosing the value of CBYP is to keep the ripple voltage on the VDD supply ≤5%. Often this is achieved w ith a value ≥ 20 times the equivalent load capacitance CEQV, defined here as Qgate/VDD. Ceramic capacitors of 0.1µF to 1µF or larger are common choices, as are dielectrics, such as X5R and X7R, w hich have good temperature characteristics and high pulse current capability. If circuit noise affects normal operation, the value of CBYP may be increased to 50-100 times the CEQV, or CBYP may be split into tw o capacitors. One should be a larger value, based on equivalent load capacitance, and the other a smaller value, such as 1-10 nF, mounted closest to the VDD and GND pins to carry the higher-frequency components of the current pulses. |
同様の部品番号 - FAN3100C |
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同様の説明 - FAN3100C |
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