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FAN3213 データシート(PDF) 15 Page - ON Semiconductor |
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FAN3213 データシート(HTML) 15 Page - ON Semiconductor |
15 / 19 page www.onsemi.com 15 Thermal Guidelines Gate dr ivers used to sw itch MOSFETs and IGBTs at high frequencies can dissipate s ignificant amounts of pow er. It is important to deter mine the driver pow er dissipation and the resulting junction temperature in the application to ensure that the part is operating w ithin acceptable temperature limits. The total pow er dissipation in a gate dr iver is the sum of tw o components, PGATE and PDYNAMIC: PTOTAL = PGATE + PDYNAMIC (1) PGATE ( Gate Driving Loss): The most significant pow er loss results from supplying gate current (charge per unit time) to sw itch the load MOSFET on and off at the sw itching frequency. The pow er dissipation that results from dr iving a MOSFET at a specified gate- source voltage, VGS, w ith gate charge, QG, at sw itching frequency, f SW, is determined by: PGATE = QG • VGS • fSW • n (2) w here n is the number of driver channels in use (1 or 2). PDYNAMIC (Dynamic Pre- Drive / Shoot-through Current): A pow er loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull-dow n resistors. The internal current consumption ( IDYNAMIC) can be estimated using the graphs in Figure 10 of the Typical Perfor mance Characteristics to deter mine the current IDYNAMIC draw n from VDD under actual operating conditions: PDYNAMIC = IDYNAMIC • VDD • n (3) w here n is the number of driver ICs in use. Note that n is usually be one IC even if the IC has tw o channels, unless tw o or more.driver ICs are in parallel to drive a large load. Once the pow er dissipated in the driver is deter mined, the driver junction rise w ith respect to circuit board can be evaluated using the follow ing ther mal equation, assuming JB w as determined for a similar ther mal design (heat sinking and air flow ): TJ = PTOTAL • JB + TB (4) w here: TJ = driver junction temperature; JB = (psi) thermal characterization parameter relating temperature rise to total pow er dissipation; and TB = board temperature in location as defined in the Thermal Characteristics table. To give a numerical example, assume for a 12 V V DD (Vibas) system, the synchronous rectifier sw itches of Figure 33 have a total gate charge of 60 nC at VGS = 7 V. Therefore, tw o devices in parallel w ould have 120 nC gate charge. At a sw itching frequency of 300 kHz, the total pow er dissipation is: PGATE = 120 nC • 7 V • 300 kHz • 2 = 0.504 W (5) PDYNAMIC = 3.0 mA • 12 V • 1 = 0.036 W (6) PTOTAL = 0.540 W (7) The SOIC-8 has a junction-to-board ther mal characterization parameter of JB = 42°C/W. In a system application, the localized temperature around the device is a function of the layout and construction of the PCB along w ith airflow across the surfaces. To ensure reliable operation, the maximum junction temperature of the device must be prevented from exceeding the maximum rating of 150°C; w ith 80% derating, TJ w ould be limited to 120°C. Rearranging Equation 4 deter mines the board temperature required to maintain the junction temperature below 120°C: TB,MAX = TJ - PTOTAL • JB (8) TB,MAX = 120°C – 0.54 W • 42°C/W = 97°C (9) |
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同様の説明 - FAN3213 |
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