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SN74CB3T16210DGGR データシート(PDF) 4 Page - Texas Instruments |
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SN74CB3T16210DGGR データシート(HTML) 4 Page - Texas Instruments |
4 / 14 page www.ti.com SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW) A EN(2) B Control Circuit VG(1) (1) Gate voltage (VG) is equal to approximately VCC + VT when the switch is ON and VI > VCC + VT. (2) EN is the internal enable signal applied to the switch. Absolute Maximum Ratings (1) SN74CB3T16210 20-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH WITH 5-V-TOLERANT LEVEL SHIFTER SCDS156A – OCTOBER 2003 – REVISED MARCH 2005 over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 7 V VIN Control input voltage range(2)(3) –0.5 7 V VI/O Switch I/O voltage range(2)(3)(4) –0.5 7 V IIK Control input clamp current VIN < 0 –50 mA II/OK I/O port clamp current VI/O < 0 –50 mA IIO ON-state switch current(5) ±128 mA Continuous current through VCC or GND ±100 mA DGG package 70 θ JA Package thermal impedance(6) °C/W DGV package 58 Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to ground unless otherwise specified. (3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (4) VI and VO are used to denote specific conditions for VI/O. (5) II and IO are used to denote specific conditions for II/O. (6) The package thermal impedance is calculated in accordance with JESD 51-7. 4 |
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