K64P144M120SF5 datasheet(10/85 Pages) NXP

部品番号	K64P144M120SF5

部品情報	Kinetis K64F Sub-Family

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Table 4. Voltage and current operating behaviors (continued)

Symbol

Description

Min.

Max.

Unit

Notes

IOZ

Hi-Z (off-state) leakage current (per pin)

—

0.25

μA

IOZ_RTC_WAK

EUP

Hi-Z (off-state) leakage current (per RTC_WAKEUP

pin)

—

0.25

μA

RPU

Internal pullup resistors (except RTC_WAKEUP pins)

20

50

kΩ

2

RPD

Internal pulldown resistors (except RTC_WAKEUP

pins)

20

50

kΩ

3

1. Measured at VDD=3.6V

2. Measured at VDD supply voltage = VDD min and Vinput = VSS

3. Measured at VDD supply voltage = VDD min and Vinput = VDD

2.2.4 Power mode transition operating behaviors

All specifications except tPOR, and VLLSx→RUN recovery times in the following table

assume this clock configuration:

• CPU and system clocks = 100 MHz

• Bus clock = 50 MHz

• FlexBus clock = 50 MHz

• Flash clock = 25 MHz

Table 5. Power mode transition operating behaviors

Symbol

Description

Min.

Max.

Unit

Notes

tPOR

After a POR event, amount of time from the point VDD

reaches 1.71 V to execution of the first instruction

across the operating temperature range of the chip.

—

300

μs

• VLLS0 → RUN

—

156

μs

• VLLS1 → RUN

—

156

μs

• VLLS2 → RUN

—

78

μs

• VLLS3 → RUN

—

78

μs

• LLS → RUN

—

4.8

μs

• VLPS → RUN

—

4.5

μs

• STOP → RUN

—

4.5

μs

General

10

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 11/2016

NXP Semiconductors

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