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ISL2111ARTZ データシート(PDF) 4 Page - Renesas Technology Corp |
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ISL2111ARTZ データシート(HTML) 4 Page - Renesas Technology Corp |
4 / 15 page ISL2110, ISL2111 FN6295 Rev.7.00 Page 4 of 15 Mar 16, 2017 Pin Configurations ISL2111ARTZ (10 LD 4x4 TDFN) TOP VIEW ISL2110AR4Z, ISL2111AR4Z (12 LD 4x4 DFN) TOP VIEW ISL2110ABZ, ISL2111ABZ (8 LD SOIC) TOP VIEW ISL2111BR4Z (8 LD 4x4 DFN) TOP VIEW 2 3 4 1 5 9 8 7 10 6 VDD HB HO HS NC LO VSS LI HI NC VDD NC NC HB HO LO V SS NC NC LI HS HI 2 3 4 1 5 11 10 9 12 8 6 7 EPAD* *EPAD = EXPOSED PAD 5 6 8 7 4 3 2 1 VDD HB HO HS LO LI HI VSS 2 3 4 1 7 6 5 8 VDD HB HO HS LO VSS LI HI EPAD* *EPAD = EXPOSED PAD Pin Descriptions SYMBOL DESCRIPTION VDD Positive supply to lower gate driver. Bypass this pin to VSS. HB High-side bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin. Bootstrap diode is on-chip. HO High-side output. Connect to gate of high-side power MOSFET. HS High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. HI High-side input LI Low-side input VSS Chip negative supply, which will generally be ground. LO Low-side output. Connect to gate of low-side power MOSFET. NC No connect EPAD Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins. |
同様の部品番号 - ISL2111ARTZ |
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同様の説明 - ISL2111ARTZ |
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