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ISL28025FI12Z-T7A データシート(PDF) 4 Page - Renesas Technology Corp |
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ISL28025FI12Z-T7A データシート(HTML) 4 Page - Renesas Technology Corp |
4 / 53 page ISL28025 FN8388 Rev.6.00 Page 4 of 53 Feb 27, 2018 Pin Configuration ISL28025 TOP VIEW 1.85SQmm EPAD A B C D 4 GND VREG _O UT VCC I2CVCC 3 VINM SM BALERT2/ ECLK A0 SM BDAT 2 VINP A2 A1 SM BCLK 1 VBUS VREG _IN AUXV SM BALERT1 ISL28025FI -- 16 Pin (BALL) 0.5mm PITCH WLCSP ISL28025FR -- 20 lead QFN 4x4 (1.85SQmm EPAD) VBUS GND AUXV DAC_OUT NC I2CVCC A2 A1 A0 GND 1 2 3 4 5 15 14 13 12 11 20 19 18 17 16 67 8 9 10 Pin Descriptions 16 Ball WLCSP 16 PIN WLCSP PIN NAME TYPE/DIR PIN DEFINITION A1 VREG_OUT Power Voltage regulator output. Connect a proper decoupling capacitor to this pin A2 VINM Analog Input Current sense minus input A3 VINP Analog Input Current sense plus input A4 VBUS Power VBus voltage sense B1 I2CVCC Power I2C level shifter power supply. Connect this pin to the VCC pin if level shifters are not used B2 VCC Power Chip power supply B3 VREG_IN Power Voltage regulator input. Connect this pin to ground if a voltage regulator is not used B4 AUXV Analog Input Auxiliary port single-ended input C1 A0 Digital Input I2C address input C2 A1 Digital Input I2C address input C3 A2 Digital Input I2C address input C4 SMBCLK Digital Input SMBus/I2C clock input D1 GND Power Ground D2 SMBALERT2/ECLK Digital Input/Output External ADC clock input or CPU interrupt signal. It is used as a CPU interrupt signal only when this pin is not configured as external clock input D3 SMBALERT1 Digital Output SMBus Alert1, open collector output D4 SMBDAT Digital Input SMBus/I2C data |
同様の部品番号 - ISL28025FI12Z-T7A |
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同様の説明 - ISL28025FI12Z-T7A |
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