ISL28023

FN8389 Rev 5.00

Page 3 of 55

March 18, 2016

Block Diagram

FIGURE 2. BLOCK DIAGRAM

FIR AND

DIGITAL

LOGIC

I

SM BUS

PM BUS

A0

16

A1

SMBCLK

SMBDAT

OSC

SMBALERT1

VINP

VINM

VBUS

GND

ADC

16-BIT

REG MAP

REF

TEMP

SENSE

OV_TEMP_SET

OC_SET

VBUS_S

3.3V

INTERNAL

POWER

AUXP

AUXM

CLO CK

UV_SET

REG

DAC_OUT

OC

DAC

OV/

TEMP

DAC

UV

DAC

I2CVCC

SMBALERT2

LS

LS

CM = 0 to 60V

CM = 0 to VCC

A2

AUXV

VREG_IN

VREG_OUT

VCC

DIV

VBUS_S

Temp_V

VBUS_S

Temp_V

ONLY FOR PRI CHL

EXT_CLK

Ordering Information

PART NUMBER

(Notes 1, 2, 3)

PART

MARKING

(V)

PACKAGE

(RoHS Compliant)

PKG.

DWG. #

ISL28023FR12Z

280 23R12Z

12

24 Ld QFN

L24.4x4D

ISL28023FR60Z

280 23R60Z

60

24 Ld QFN

L24.4x4D

ISL28023EVAL1Z

Evaluation Board

ISL28023EVKIT1Z

Evaluation Kit

NOTES:

1. Add “-T” suffix for 6k unit or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28023. For more information on MSL please see techbrief TB363.