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NB3L202K データシート(PDF) 3 Page - ON Semiconductor |
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NB3L202K データシート(HTML) 3 Page - ON Semiconductor |
3 / 14 page NB3L202K www.onsemi.com 3 Table 1. PIN DESCRIPTION Pin Number Pin Name I/O Description 1 GND Power Ground 2 CLK_IN I, DIF Differential True input 3 CLK_IN# I, DIF Differential Complementary input 4 VDD Power Core power supply 5 GND_O Power Ground for outputs 6 DIF_1# O, DIF 0.7 V Differential Complementary Output 7 DIF_1 O, DIF 0.7 V Differential True Output 8 VDD_O Power Power supply for outputs 9 GND Power Ground 10 IREF I A precision resistor is attached to this pin to set the differential output current. Use RREF = 475 W, 1% for 100 W trace, with 50 W termination. Use RREF = 412 W, 1% for 85 W trace, with 43 W termination. 11 OE0# I , SE LVTTL / LVCMOS active low input for enabling output DIF_0/0#. 0 enables outputs, 1 disables outputs. Internal pull down. 12 OE1# I , SE LVTTL / LVCMOS active low input for enabling output DIF_1/1#. 0 enables outputs, 1 disables outputs. Internal pull down. 13 VDD_O Power Power supply for outputs 14 DIF_0 O, DIF 0.7 V Differential True Output 15 DIF_0# O, DIF 0.7 V Differential Complementary Output 16 GND_O Power Ground for outputs EP Exposed Pad Thermal The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to the die, and must be electri- cally and thermally connected to GND on the PC board. |
同様の部品番号 - NB3L202K_18 |
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同様の説明 - NB3L202K_18 |
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