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LMX2323 データシート(PDF) 9 Page - National Semiconductor (TI) |
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LMX2323 データシート(HTML) 9 Page - National Semiconductor (TI) |
9 / 12 page 2.0 Programming Description (Continued) 2.3 N REGISTER If the address bit is LOW (ADDR = 0), when LE is transitioned high, data is transferred from the 18-bit shift register into the 17-bit N register. The N register consists of the 5-bit swallow counter (A counter), the 10-bit programmable counter (B counter) and the control word. Serial data format is shown below in 2.3.1 5-Bit Swallow Counter Divide Ratio (A Counter) and 2.3.2 10-Bit Programmable Counter Divide Ratio (B Counter). The pulse swallow function which determines the divide ratio is described in section 2.3.3 Pulse Swallow Function. First Bit SHIFT REGISTER BIT LOCATION Last Bit 17 16 15 14 13 12 11 10 9 8 7654 3 2 1 0 NB_CNTR [9:0] NA_CNTR [4:0] CTL_WORD [1:0] 0 DS101362-5 www.national.com 9 |
同様の部品番号 - LMX2323 |
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同様の説明 - LMX2323 |
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