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NV25080LV データシート(PDF) 8 Page - ON Semiconductor

部品番号 NV25080LV
部品情報  EEPROM Serial 8/16/32/64-Kb SPI Low
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メーカー  ONSEMI [ON Semiconductor]
ホームページ  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NV25080LV データシート(HTML) 8 Page - ON Semiconductor

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NV25080LV, NV25160LV, NV25320LV, NV25640LV
www.onsemi.com
8
Figure 6. Page WRITE Timing
SCK
SI
SO
00
00
0
1
0
BYTE ADDRESS*
Data
Byte 1
0123
456
78
21 22 23 24−31 32−39
Data Byte N
OPCODE
7..1
0
24+(N−1)x8−1 .. 24+(N−1)x8
24+Nx8−1
DATA IN
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
CS
AN
A0
Data
Byte 3
Data
Byte 2
0
* Please check the Byte Address Table (Table 11)
Write Status Register
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 7. Only bits
2, 3, 4, 6 and 7 can be written using the WRSR command.
Write Protection
The Write Protect (WP) pin can be used to protect the
Block Protect bits BP0 and BP1 against being inadvertently
altered. When WP is low and the WPEN bit is set to “1”,
write operations to the Status Register are inhibited. WP
going low while CS is still low will interrupt a write to the
status register. If the internal write cycle has already been
initiated, WP going low will have no effect on any write
operation to the Status Register. The WP pin function is
blocked when the WPEN bit is set to “0”.
Figure 7. WRSR Timing
01
2
3
4
5
6
7
8
10
911
12
13
14
SCK
SI
MSB
HIGH IMPEDANCE
DATA IN
15
SO
7
6
5
4
3
2
10
00
0
0
0
0
0
1
OPCODE
Dashed Line = mode (1, 1)
CS


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