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データシートサーチシステム |
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データシートサーチシステム |
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NV25080LV データシート(PDF) 9 Page - ON Semiconductor |
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NV25080LV データシート(HTML) 9 Page - ON Semiconductor |
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9 / 20 page  NV25080LV, NV25160LV, NV25320LV, NV25640LV www.onsemi.com 9 READ OPERATIONS Read from Memory Array To read from memory, the host sends a READ instruction followed by a 16−bit address (see Table 11 for the number of significant address bits). After receiving the last address bit, the NV25xxx will respond by shifting out data on the SO pin (as shown in Figure 8). Sequentially stored data can be read out by simply continuing to run the clock. The internal address pointer is automatically incremented to the next higher address as data is shifted out. After reaching the highest memory address, the address counter “rolls over” to the lowest memory address, and the read cycle can be continued indefinitely. The read operation is terminated by taking CS high. Read Status Register To read the status register, the host simply sends a RDSR command. After receiving the last bit of the command, the NV25xxx will shift out the contents of the status register on the SO pin (Figure 9). The status register may be read at any time, including during an internal write cycle. While the internal write cycle is in progress, the RDSR command will output the full content of the status register. For easy detection of the internal write cycle completion, we recommend sampling the RDY bit only through the polling routine. After detecting the RDY bit “0”, the next RDSR instruction will always output the expected content of the status register. Read Identification Page Reading the additional 32−byte Identification Page (IP) is achieved using the same Read command sequence as used for Read from main memory array (Figure 8). The IPL bit from the Status Register must be set (IPL = 1) before attempting to read from the IP. The [A4:A0] are the address significant bits that point to the data byte shifted out on the SO pin. If the CS continues to be held low, the internal address register defined by [A4:A0] bits is automatically incremented and the next data byte from the IP is shifted out. The byte address must not exceed the 32−byte page boundary. Figure 8. READ Timing SCK SI SO BYTE ADDRESS* 012 3456 78 9 7 6 5 4 3 2 1 0 DATA OUT MSB HIGH IMPEDANCE OPCODE 21 20 22 23 24 25 26 27 28 29 30 00 00 0 1 1 Dashed Line = mode (1, 1) A0 AN CS * Please check the Byte Address Table (Table 11) 0 10 Figure 9. RDSR Timing 01 2 3 4 5 6 7 8 10 911 12 13 14 SCK SI DATA OUT MSB HIGH IMPEDANCE OPCODE SO 7 6 5 4 3 2 1 0 00 0 0 0 1 0 1 Dashed Line = mode (1, 1) CS |
同様の部品番号 - NV25080LV |
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同様の説明 - NV25080LV |
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