REV. B

AD8315

–10–

Control Loop Dynamics

In order to understand how the AD8315 behaves in a complete

control loop, an expression for the current in the integration

SETPOINT

INTERFACE

LOGARITHMIC

RF DETECTION

SUBSYSTEM

3

1

RFIN

4

FLTR

7

VAPC

1.35

Figure 3. Behavioral Model of the AD8315

First, the summed detector currents are written as a function of

the input:

II

V

V

DET

SLP

IN

Z

=

log

(

/

)

10

(3)

exact average value will be extracted through the subsequent

of 115

previously noted, is dependent on waveform but is 316

mV rms

(–70 dBV) for a sine wave input. Now the current generated by

the setpoint interface is simply:

IV

k

SET

SET

=W

/.

415

(4)

Vs

I

I

sC

FLT

SET

DET

FLT

()

(

–

)/

=

(5)

=

W

Vk

I

V

V

sC

SET

SLP

IN

Z

FLT

/.

–

log

(

/

)

415

10

(6)

gain of the output buffer is

¥1.35. Also, an offset voltage is

deliberately introduced in this stage; this is inconsequential

since the integration function implicitly allows for an arbitrary

constant to be added to the form of Equation 6. The polarity is

unless the control loop through the power amplifier is present.

In other words, the AD8315 seeks to drive the RF power to its

maximum value whenever it falls below the setpoint. The use

of exact integration results in a final error that is theoretically

zero, and the logarithmic detection law would ideally result in a

constant response time following a step change of either the

setpoint or the power level, if the power-amplifier control

function were likewise linear-in-dB. This latter condition is

rarely true, however, and it follows that in practice, the loop

response time will depend on the power level, and this effect can

strongly influence the design of the control loop.

Equation 6 can be restated as:

Vs

VV

V

V

sT

APC

SET

SLP

IN

Z

()

log

(

/

)

=

-

10

(7)

a value of 480 mV/decade, and T is an effective time constant for

the integration, being equal to 4.15 k

value comes from the setpoint interface scaling Equation 4 and

the factor 1.35 arises because of the voltage gain of the buffer.

So the integration time constant can be written as:

TC

in s when C is

in nF

FLT

= 307

.,

m

expressed

(8)

To simplify our understanding of the control loop dynamics,

begin by assuming that the power amplifier gain function actu-

ally is linear-in-dB. Also use voltages to express the signals at

the power amplifier input and output, for the moment. Let the

characterize the gain control function, this form is used:

VG V

PA

O

CW

VV

APC

GBC

=

10

(/)

(9)

conveniently to this law, it provides a clearer starting point for

understanding the more complex situation that arises when the

gain control law is less ideal.

This idealized control loop is shown in Figure 4. With some

manipulation, it is found that the characteristic equation of this

system is:

Vs

VV

V

V

kG V

V

sT

APC

SET

GBC

SLP

GBC

O

CW

Z

O

()

()/

–

log

/

=

()

+

10

1

(10)

where k is the coupling factor from the output of the power

amplifier to the input of the AD8315 (e.g.,

¥ 0.1 for a “20 dB

This is quite easy to interpret. First, it shows that a system of

this sort will exhibit a simple single-pole response, for any power

level, with the customary exponential time domain form for

either increasing or decreasing step polarities in the demand

several fixed factors:

Vt

V

V

V

kG V

V

APC

SET

GBC

SLP

O

CW

Z

=•

(

)

/– log

/

10

(11)

Example

Assume that the gain magnitude of the power amplifier runs

from a minimum value of

30 dB directional coupler) and recalling that the nominal value of

of 33 dBm to –17 dBm. This can be found by noting that, in

the steady state, the numerator of Equation 7 must be zero,

that is:

VV

kV

V

SET

SLP

PA

Z

=

log

(

/

)

10

(12)

this evaluates to:

VmV

V

V

.

log

(

/

)

.

max

==

048

316

316

1 44

10

m

(13)

VmV

V

V

.

log

(

/

)

.

min

==

048

1

316

024

10

m

(14)