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ST19WP18 データシート(PDF) 2 Page - STMicroelectronics

部品番号 ST19WP18
部品情報  Trusted Platform Module (TPM)
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST19WP18 データシート(HTML) 2 Page - STMicroelectronics

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ST19WP18
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GENERAL DESCRIPTION
The ST19WP18 is a cost effective Trusted Plat-
form Module (TPM) solution. The ST19WP18 is
designed to provide PC platforms with enhanced
security and integrity mechanisms as defined by
Trusted Computing Group standards. The product
provides full support of TCG v1.1b as well as TCG
v1.2 specifications
The ST19WP18 is driven from the Smartcard IC
ST19W platform. It is manufactured using the ad-
vanced highly reliable STMicroelectronics CMOS
EEPROM technology.
The ST19WP18 has an 8-bit CPU architecture
and includes the following on-chip memories:
User ROM, User RAM and EEPROM with state of
the art security features. ROM, RAM and EEP-
ROM memories can be configured into partitions
with customized access rules.
The ST19WP18 also includes a Modular Arithme-
tic Processor (MAP). The 1088 bits architecture of
this cryptographic engine allows processing of
modular multiplication, squaring and additional
calculations up to 2176 bit operands.
The Modular Arithmetic Processor is designed to
speed up cryptographic calculations using Public
Key Algorithms.
The Secure Hash Accelerator allows fast SHA-1
computation especially well suited for BIOS hash
operations during early boot stages.
The ST19WP18 has been specially designed in
line with TCG PC Client Specific TPM Implemen-
tation Specification (TIS) referring to Intel’s LPC
Specification revision 1.0.
Figure 2. Block Diagram
INTERNAL BUS
MEMORY ACCESS FIREWALL
I/O0
1 x
Serial
interface
Gnd 2
8 bit
CPU
3 x
8 bit
Timers
CRC
module
CLK
Clock
Generator
module
ST ROM, MAP and DES FIREWALL
RAM
User ROM
ST ROM, RF
and Crypto
Libraries
EDES
Accelerator
MAP
1088 bits
514
Vcc 2
Gun A
&
Gun B
Security
Admin.
RESET
EEPROM
SHA
Module
5 x
General
purpose
I/Os
interface
Gpi/0
RAM 2K
LPC
interface
LFrame LPCPD
Lad3
Lad2
Lad1
Lad0
PP
SERIRQ
VBAT


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