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SMH4042AGBGN データシート(PDF) 3 Page - Summit Microelectronics, Inc. |
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SMH4042AGBGN データシート(HTML) 3 Page - Summit Microelectronics, Inc. |
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3 / 28 page  2070 9.1 5/27/03 SMH4042A SUMMIT MICROELECTRONICS, Inc. 3 A0 (8) Address 0 is not used by the memory array. It can be connected to ground or left floating. It must not be connected VCC. A1, A2 (10, 11) Address inputs 1 and 2 are used to set the two-bit device address of the memory array. The state of these inputs will determine the device address for the memory if it is on a two-wire bus with multiple memories with the same device type identifier. SCL (19) The SCL input is used to clock data into and out of the memory array. In the write mode, data must remain stable while SCL is HIGH. In the read mode, data is clocked out on the falling edge of SCL. SDA (18) The SDA pin is a bidirectional pin used to transfer data into and out of the memory array. Data changing from one state to the other may occur only when SCL is LOW, except when generating START or STOP conditions. SDA is an open-drain output and may be wire-ORed with any number of open-drain outputs. CARD_3V_MON (21) This input monitors the card-side 3.3V supply. If the input falls below VTRIP then the HEALTHY# and SGNL_VLD# outputs are de-asserted and the reset outputs are driven active. CARD_5V_MON (25) This input monitors the card-side 5V supply. If the input falls below VTRIP then the HEALTHY# and SGNL_VLD# outputs are de-asserted and the reset outputs are driven active. CBI_3 (24) CBI_3 is the circuit breaker input for the low supply. With a series resistor placed in the supply path between VCC3 and CBI_3, the circuit breaker will trip whenever the voltage across the resistor exceeds 50mV. CBI_5 (1) CBI_5 is the circuit breaker input for the supply voltage. With a series resistor placed in the supply path between the 5V early power and CBI_5, the circuit breaker will trip whenever the voltage across the resistor exceeds 50mV. PIN DESCRIPTIONS HST_3V_MON (23) This input monitors the host 3.3V supply and it is used as a reference for the circuit breaker comparator. If VCC3 falls below VTRIP then SGNL_VLD# is de-asserted, the high side drivers are disabled, and LOCAL_PCI_RST# is asserted. ISLEW (3) A Diode-connected NFET input. It may be used to adjust the 250V/s default slew rate of the high-side driver outputs. PCI_RST# (17) A TTL level reset input signal from the host interface. A high to low transition (held low longer than 40ns) will initiate a reset sequence. The LOCAL_PCI_RST# and LOCAL_PCI_RST outputs will be driven active for a minimum period of tPURST. If the PCI_RST# input is still held low after tPURST times out the reset outputs will continue to be driven until PCI_RST# is released. PWR_EN (7) A TTL level input that allows the host to enable or disable the power to the individual card. During initial power up this signal would start in a low state, and then be driven high during software initialization. If this signal is driven low then the power supply control outputs will be driven into the inactive state and the reset signals asserted. In a “non-High Availability” system this input can be tied high. The PWR_EN input is also used to reset the SMH4042A circuit breakers. After an over-current condi- tion is detected the VGATE outputs can be turned back on by first taking PWR_EN low then returning it high. VSEL (6) A TTL level input used to determine which of the host power supply inputs will be monitored for valid voltage and reset generation. This is a static input and the pin should be tied to VCC or ground through a resistor. VSEL is high for 3.3V power. VSEL is low for 5V or mixed mode power. VCC (28) The power supply input. It is monitored for power integrity. If it falls below the 5V sense threshold (VTRIP) and the VSEL input is low then the SGNL_VLD# and HEALTHY# signals are de-asserted, the high side drivers disabled, and reset outputs asserted. On a CompactPCI board this must be connected to early power. |
同様の部品番号 - SMH4042AGBGN |
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同様の説明 - SMH4042AGBGN |
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